Partial-PreSET: Enhancing Lifetime of PCM-Based Main Memory with Fine-Grained SET Operations

Abstract

Phase change memory (PCM) is one of promising technology to replace DRAM with its attractive features such as zero leakage power and high scalability. In PCM, a SET operation needs much more time than a RESET operation. A typical write request concurrently writes 64 bytes to a PCM memory line. Therefore, write latency is mainly determined by SET operations. Previously, PreSET has been proposed to improve PCM performance by exploiting asymmetry in write time. A PreSET operation pro-actively SETs all the bits in the memory line before a dirty cache line is written to PCM . Later, when a write request is processed, only RESET operations are actually performed. Consequently, PreSET reduces write latency and improves system performance. However, such PreSET operations are conducted only at a very coarse-grained level, which reduces the endurance of PCM. Through empirical study, we observe that in most applications the number of dirty words in a dirty line is actually quite limited. If we only SET those dirty words, instead of the whole cache line, we would significantly extend the lifetime of PCM while still achieving desirable performance. Inspired by this observation, we propose a scheme called Partial-PreSET which balances performance and endurance of PCM. The core idea of this scheme is to SET those dirty bits of a cache line in a fine-grained fashion. Our experiments show that the proposed Partial-PreSET scheme significantly improves the average lifetime of PCM system, up to 2.79X, while incurring only 2% system performance loss, compared with the state-of-the-art scheme (i.e., PreSET).