Abstract
The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The memory-side power savings using compression are easily lost on inefficient fetch unit design. We propose an implementation for instruction template-based compression and two instruction fetch alternatives for variable length instruction encoding on transport triggered architecture, a static multiple-issue exposed data path architecture. With applications from the CHStone benchmark suite, the compression approach reaches an average compression ratio of 44% at best. We show that the variable length fetch designs reduce the number of memory accesses and often allow the use of a smaller memory component. The proposed compression scheme reduced the energy consumption of synthesized benchmark processors by 15% and area by 33% on average.
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References
Corporaal, H.: Microprocessor Architectures: From VLIW to TTA. Wiley, Chichester (1997)
Deepaksubramanyan, B.S., Nun̋ez, A.: Analysis of subthreshold leakage reduction in CMOS digital circuits. In: Proc. Midwest Symp. Circ. Syst., pp. 1400–1404. Montreal, QC (2007). https://doi.org/10.1109/MWSCAS.2007.4488809
Esko, O., Jääskeläinen, P., Huerta, P., de La Lama, C., Takala, J., Martinez, J.: Customized exposed datapath soft-core design flow with compiler support. In: Proc. Int. Conf. Field Programmable Logic and Applications, pp. 217–222. Milan, Italy (2010). https://doi.org/10.1109/FPL.2010.51
Hara, Y., Tomiyama, H., Honda, S., Takada, H.: Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. J. Inf. Process. 17, 242–254 (2009). https://doi.org/10.2197/ipsjjip.17.242
He, Y., She, D., Mesman, B., Corporaal, H.: MOVE-Pro: a low power and high code density TTA architecture. In: Proc. Int. Conf. Embedded Comput. Syst.: Architectures, Modeling and Simulation, pp. 294–301. Samos, Greece (2011)
Heikkinen, J.: Program compression in long instruction word application-specific instruction-set processors. Ph.D. thesis, Tampere Univ. Tech., Finland (2007)
Heikkinen, J., Takala, J., Corporaal, H.: Dictionary-based program compression on customizable processor architectures. Microprocess. Microsyst. 2, 139–153 (2009)
Helkala, J., Viitanen, T., Kultala, H., Jääskeläinen, P., Takala, J., Zetterman, T., Berg, H.: Variable length instruction compression on Transport Triggered Architectures. In: Proc. Int. Conf. Embedded Comput. Syst.: Architectures, Modeling and Simulation, pp. 149–155. Samos, Greece (2014)
Jääskeläinen, P., Guzma, V., Cilio, A., Takala, J.: Codesign toolset for application-specific instruction-set processors. In: Proc. SPIE Multimedia on Mobile Devices, pp. 65,070X–1 – 65,070X–11. San Jose, USA (2007)
Kultala, H., Viitanen, T., Jääskeläinen, P., Helkala, J., Takala, J.: Compiler optimizations for code density of variable length instructions. In: Proc. IEEE Workshop on Signal Processing Systems, pp. 1–6. Belfast, UK (2014)
Pan, H., Asanović, K.: Heads and tails: a variable-length instruction format supporting parallel fetch and decode. In: Proc. Int. Conf. Compilers Arch. Synthesis for Embedded Syst., pp. 168–175. Atlanta, Georgia (2001). https://doi.org/10.1145/502217.502244
Pilo, H., Adams, C.A., Arsovski, I., Houle, R.M., Lamphier, S.M., Lee, M.M., Pavlik, F.M., Sambatur, S.N., Seferagic, A., Wu, R., Younus, M.I.: A 64 Mb SRAM in 22 nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. In: Proc. IEEE Int. Solid-State Circ. Conf. Digest Tech. Papers, pp. 322–323. San Francisco, USA (2013). https://doi.org/10.1109/ISSCC.2013.6487753
Schlansker, M.S., Rau, B.R.: EPIC: An Architecture for Instruction-Level Parallel Processors. Tech. rep, Hewlett-Packard (2000)
Segars, S., Clarke, K., Goudge, L.: Embedded control problems, thumb, and the ARM7TDMI. IEEE Micro 15(5), 22–30 (1995). https://doi.org/10.1109/40.464580
Shahabuddin, S., Janhunen, J., Bayramoglu, M.F., Juntti, M., Ghazi, A., Silvén, O.: Design of a unified transport triggered processor for LDPC/turbo decoder. In: Proc. Int. Conf. Embedded Comput. Syst.: Architectures, Modeling and Simulation, pp. 288–295. IEEE (2013)
Sheng, L., Ahn, J.H., Strong, R., Brockman, J., Tullsen, D., Jouppi, N.: McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. In: Proceedings of Annual International Symposium on Microarchitecture, pp. 469–480. New York, USA (2009)
Thoziyoor, S., Ahn, J.H., Monchiero, M., Brockman, J.B., Jouppi, N.P.: A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies. In: Proc. ACM/IEEE Int. Symp. Comp. Arch., pp. 51–62. Beijing, China (2008)
Viitanen, T., Kultala, H., Jaaskelainen, P., Takala, J.: Heuristics for greedy transport triggered architecture interconnect exploration. In: Proc. Int. Conf. Compilers, Architecture and Synthesis for Embedded Systems, pp. 1–7 (2014)
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The authors would like to thank Business Finland (funding decisions 40081/14 and 1846/31/2014), Academy of Finland (funding decisions 253087 and 297548), and ARTEMIS JU under Grant Agreement No. 621439 (ALMARVI)
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Viitanen, T., Helkala, J., Kultala, H. et al. Variable Length Instruction Compression on Transport Triggered Architectures. Int J Parallel Prog 46, 1283–1303 (2018). https://doi.org/10.1007/s10766-018-0568-8
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DOI: https://doi.org/10.1007/s10766-018-0568-8