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Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation

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Abstract

To preserve the SystemC semantics under parallel discrete event simulation, a compiler based approach statically analyzes race conditions in the design model. However, there are severe restrictions: the source code for the input design must be available in one file, which does not scale. This disables the use of intellectual property (IP) and hierarchical file structures. This paper scales the static analysis design flow to support separate files and IP reuse by introducing partial segment graph and partial port mapping abstractions and prevent IP security leakage. Experiments demonstrate the effective design flow and sustained speedup with parallel IPs.

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Acknowledgements

This work has been supported in part by substantial funding from Intel Corporation for the project titled “Scaling the Recoding Infrastructure for Parallel SystemC Simulation”. The authors thank Intel Corporation for the valuable support.

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  1. University of California, Irvine, USA

    Zhongqi Cheng, Tim Schmidt & Rainer Dömer

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  1. Zhongqi Cheng
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Correspondence to Zhongqi Cheng.

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Cheng, Z., Schmidt, T. & Dömer, R. Scaled Static Analysis and IP Reuse for Out-of-Order Parallel SystemC Simulation. Int J Parallel Prog 49, 200–215 (2021). https://doi.org/10.1007/s10766-020-00668-w

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  • DOI: https://doi.org/10.1007/s10766-020-00668-w

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