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DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures

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Abstract

Embedded system applications, with their inherently limited parallelism, rarely exploit all available processing resources in large DSM-based manycore architectures. From a cache coherence perspective, this provides an opportunity to move away from global coherence spanning across all tiles, which does not scale well. Therefore, we favor a region-based cache coherence (RBCC) approach that enables coherence among a selectable cluster of tiles in accordance with application requirements. We present the design and hardware implementation of a flexibly configurable coherency region manager (CRM) that enables RBCC. We introduce two novel features that enhance RBCC, namely, runtime coherency region re-configuration and RBCC-malloc(), that dynamically tailor coherence to actually shared application working sets. Further, we propose, implement and evaluate additional CRM functions such as a non-intrusive barrier synchronization mechanism and a false sharing resolution strategy for our DSM-based manycore architecture. We have synthesized the CRM on an FPGA prototype for a 64-core system and observe a 38% reduction in BRAM-utilization compared to a global coherence directory for regions with up to 32 cores. Experiments using a video streaming application reveal a speed-up of up to 42% compared to an alternative message passing based implementation. We also evaluate the benefits of runtime coherency region re-configuration using two scenarios and present a formal analysis on when a re-configuration is beneficial.

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Notes

  1. In our system, coherence and their acknowledgement messages are not re-ordered.

  2. Multiple coherence barriers can be supported by increasing the number of barrier and shadow registers per tile.

  3. For some applications, this can additionally contain state transfers.

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Acknowledgements

This work was partly funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation)—Project Number 146371743-TRR 89: Invasive Computing.

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  1. Technical University of Munich, Munich, Germany

    Akshay Srivatsa, Mostafa Mansour, Sven Rheindt, Dirk Gabriel, Thomas Wild & Andreas Herkersdorf

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  1. Akshay Srivatsa
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  2. Mostafa Mansour
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  3. Sven Rheindt
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  5. Thomas Wild
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Correspondence to Akshay Srivatsa.

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Conflict of interest

The authors would like to thank Sai Varun Brahmadevara, Li-Yu Peng and Miguel Montoya Rendon for their contributions as master and internship students at the Chair of Integrated Systems, TUM. We would also like to thank Sebastian Maier at the Computer Science 4 department, FAU, Erlangen-Nuremberg for his OS support.

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Srivatsa, A., Mansour, M., Rheindt, S. et al. DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. Int J Parallel Prog 49, 570–599 (2021). https://doi.org/10.1007/s10766-020-00688-6

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