The General Packet Radio Service (GPRS) was developed to allow packet data to be transported efficiently over an existing circuit switched radio network. The main applications for GPRS are in transporting IP datagram’s from the user’s mobile Internet browser to and from the Internet, or in telemetry equipment. A simple Error Detection and Correction (EDC) scheme to improve the GPRS Block Error Rate (BLER) performance is presented, particularly for coding scheme 4 (CS-4), however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel, improving throughput and the user’s application data rate. As GPRS requires intensive processing in the baseband, a viable hardware solution for a GPRS BLER co-processor is discussed that has been currently implemented in a Field Programmable Gate Array (FPGA) and presented in this paper.
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The contribution of DSP development hardware and host software is gratefully acknowledged from Texas Instruments on behalf of Robert Owen, University Programme Manager: Education & Communications of the Texas Instruments European University Programme.
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When this work was completed and now Kai Zhang is with Current affiliation: Beijing Kedong Power Control System Co. Ltd.
When this work was completed and now Owen J. Wilkes is with Current affiliation: Aculab.
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Sherratt, R.S., Zhang, K. & Wilkes, O.J. Improving CS-4 User Data Rate in GPRS Enabled Devices by Using a BLER Co-processor. Int J Wireless Inf Networks 13, 239–251 (2006). https://doi.org/10.1007/s10776-005-0013-y
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DOI: https://doi.org/10.1007/s10776-005-0013-y