Abstract
Design of Turbo-Code decoders for the 3GPP LTE/LTE-A standard focuses on achieving a high-throughput of up to 1 Gbps with low decoding latencies at very high code rates. At code rates close to one, as specified in LTE/LTE-A, the decoding process can oscillate. Although the decoder converges to a valid code word after half-iteration i, after half-iteration \(i+1\) the decoded code word is invalid again. To circumvent this, the CRC that is attached to each code word must be evaluated after each half-iteration. We present a generalized architecture for calculating the CRC On-the-fly during both non-interleaved and interleaved half-iterations and thus explicitly taking into account the requirements for low-latency Turbo-Code decoding. Further, we investigate the latency-, and energy savings provided by employing this calculation scheme. Lastly, we give post layout synthesis results for a case study implementation in state-of-the-art 28 nm FDSOI technology.
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Third Generation Partnership Project, LTE; Evolved Universal Terrestrial Radio Access (E-UTRA); Physical layer procedures (3GPP TS 36.213 version 12.4.0 Release 12), February 2015.
M. May, T. Ilnseher, N. Wehn, and W. Raab, A 150 Mbit/s 3GPP LTE Turbo Code Decoder. In Proc. Design, Automation and Test in Europe, 2010 (DATE ’10), pages 1420–1425, March 2010.
S. Weithoffer and N. Wehn, Latency reduction for LTE/LTE-A turbo-code decoders by on-the-fly calculation of CRC. In 2015 IEEE 26th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pages 1409–1414, Aug 2015.
W. W. Peterson and D. T. Brown, Cyclic codes for error detection, Proceedings of the IRE, Vol. 49, No. 1, pp. 228–235, 1961.
M. Sprachmann, Automatic generation of parallel CRC circuits, IEEE Design Test of Computers, Vol. 18, No. 3, pp. 108–114, 2001.
Y. Sun and M. S. Kim, A pipelined CRC calculation using lookup tables. In Consumer Communications and Networking Conference (CCNC), 2010 7th IEEE, pages 1–2, Jan 2010.
Y. Lin, H. Lee, M. Who, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, and K. Flautner, SODA: a low-power architecture for software radio. In Proceedings of 33rd International Symposium on Computer Architecture ISCA ’06, pages 89–101, 2006.
C. Cheng and K. K. Parhi, High-speed parallel CRC implementation based on unfolding, pipelining, and retiming. IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 53, No. 10, pp. 1017–1021, 2006.
S. Singh, S. Sujana, I. Babu, and K. Latha, VLSI implementation of parallel CRC using pipelining, unfolding and retiming. IOSR Journal of VLSI and Signal Processing, Vol. 2, No. 5, pp. 66–72, 2013.
H. Michael Ji and E. Killian, Fast parallel CRC algorithm and implementation on a configurable processor. In IEEE International Conference on Communications, 2002. ICC 2002, Vol. 3, pages 1813–1817. IEEE, 2002.
H. Kim and J.-H. Kim,Design of early stopping unit in parallel turbo decoder based on galois field operation. In SoC Design Conference (ISOCC), 2013 International, pages 050–051, Nov 2013.
H. Kim, I. Choi, W. Byun, J.-Y. Lee and J.-H. Kim, Distributed CRC architecture for high-radix parallel turbo decoding in LTE-advanced systems, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 9, pp. 906–910, 2015.
C. Condo, M. Martina, G. Piccinini, and G. Masera, Variable parallelism cyclic redundancy check circuit for 3GPP-LTE/LTE-advanced. IEEE Signal Processing Letters, Vol. 21, No. 11, pp. 1380–1384, 2014.
H. Kim, Y. Lee, and J. H. Kim, Low-complexity CRC-aided early stopping unit for parallel turbo decoder. Electronics Letters, Vol. 51, No. 21, pp. 1660–1662, 2015.
S. Belfanti, C. Roth, M. Gautschi, C. Benkeser, and Q. Huang, A 1 Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS. In 2013 Symposium on VLSI Circuits (VLSIC), pages C284–C285, June 2013.
P. Robertson, E. Villebrun, and P. Hoeher, A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log-domain. In Proceedings of 1995 International Conference on Communications (ICC ’95), pages 1009–1013, Seattle, Washington, USA, June 1995.
M. Bickerstaff, L. Davis, C. Thomas, D. Garrett, and C. Nicol, A 24Mb/s Radix-4 LogMAP Turbo Decoder for 3GPP-HSDPA mobile wireless. In Proceedings of 2003 IEEE International Solid-State Circuits Conference (ISSCC ’03), pages 150–151,484, San Francisco, CA, USA, February 2003.
T. Ilnseher, F. Kienle, C. Weis, and N. Wehn, A 2.12Gbit/s Turbo Code Decoder for LTE advanced base station applications. In 2012 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) (ISTC 2012), Gothenburg, Sweden, August 2012.
Y. Sun and J. R. Cavallaro, Unified decoder architecture for LDPC/turbo codes. In Proceedings of IEEE Workshop on Signal Processing Systems SiPS 2008, pages 13–18, October 2008.
J. Dielissen and J. Huiskens, State vector reduction for initialization of sliding windows MAP. In Proceedings of 2nd International Symposium on Turbo Codes & Related Topics, pages 387–390, Brest, France, September 2000.
T. Ilnseher, M. May, and N. Wehn, A monolithic LTE interleaver generator for highly parallel SMAP decoders. In Proceedings of Tenth Annual Wireless Telecommunications Symposium (WTS 2011), April 2011.
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Weithoffer, S., Wehn, N. Low-Latency CRC Calculation in Turbo-Code Decoding. Int J Wireless Inf Networks 25, 98–107 (2018). https://doi.org/10.1007/s10776-017-0374-z
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DOI: https://doi.org/10.1007/s10776-017-0374-z