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Memory Defect Tolerance Architectures for Nanotechnologies

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Abstract

Memory Built In Self Repair (BISR) is gaining importance since several years. Because defect densities are increasing in future submicron technologies, more advanced solutions may be required for memories to be produced in the upcoming nanometric CMOS process generations. Moreover, this problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels of several orders of magnitude higher than in current CMOS technologies. For such defect densities, traditional memory repair is not adequate. This work presents several Built-In Self Repair techniques addressing memories affected by high defect densities as well as an evaluation of the area cost and yield. Statistical fault injection simulations were conducted and the obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost. Thus, the extreme defect densities that many authors predict for nanotechnologies do not represent a show-stopper, at least as concerning memories.

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Authors and Affiliations

  1. iRoC Technology, Grenoble, France

    Michael Nicolaidis

  2. TIMA Laboratory, Grenoble, France

    Lorena Anghel

  3. Synopsys, Grenoble, France

    Nadir Achouri

Authors
  1. Michael Nicolaidis
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  2. Lorena Anghel
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  3. Nadir Achouri
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Nicolaidis, M., Anghel, L. & Achouri, N. Memory Defect Tolerance Architectures for Nanotechnologies. J Electron Test 21, 445–455 (2005). https://doi.org/10.1007/s10836-005-0971-0

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  • DOI: https://doi.org/10.1007/s10836-005-0971-0

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