Abstract
This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter.
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References
Agilent Technologies Inc., http://www.agilent.com.
Agilent Technologies Inc., “Agilent 93000 SOC Series NP—Models Technique Specifications,” pp. 5, Jul. 2002.
S.S. Akbay, A. Halder, A. Chatterjee, and D. Keezer, “Low-Cost Test of Embedded RF/Analog/Mixed-Signal Circuits in SOPs,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, 2004.
M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers, pp. 47–48, 2000
W. Dalal and M. Song, “The Value of Tester Accuracy,” in Proc. of International Test Conference, 1999, pp. 518–523.
K. Helmreich, “Test Path Simulation and Characterization,” in Proc. of International Test Conference, 2001, pp. 415–423.
Hypertransport Technology Consortium, “Hypertransport I/O Link Specification Revision 1.03,” pp. 187–193, Oct. 2001.
International Technology Roadmap for Semiconductors, 1999 Edition: Test and Test Equipment,” 1999, pp. 61–62.
International Technology Roadmap for Semiconductors, 2003 Edition: “Test and Test Equipment,” pp. 5–6, 2001.
International Technology Roadmap for Semiconductors, 2001 Edition: “Test and Test Equipment,” pp. 3–4, 2003.
C.S. Li, K.N. Sivarajan, and D.G. Messerschmitt, “Statistical analysis of timing rules for high-speed synchronous VLSI systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 4, pp. 477–482, 1999.
S.R. Naidu, “Timing yield calculation using an impulse-train approach,” in Proc. of 7th Asia and South Pacific and the 15th International Design Automation Conference, 2002, pp. 219–224.
A. Oshima, J. Poniatowski, and T. Nomura, “Pin Electronics IC for High Speed Differential Devices,” in Proc. International Test Conference, 2001, pp. 1128–1133.
A. Papoulis, Probability, Random Variables, and Stochastic Processes, 2nd edition. New York: McGraw-Hill, 1984, pp. 100–101.
E.S. Park, M.R. Mercer, and T.W. Williams, “The total delay fault model and statistical delay fault coverage,” IEEE Transactions on Computers, vol. 41, no. 6, pp. 688–698, 1992.
PCISIG, “PCI Express Base Specification Revision 1.0,” July 22, 2002.
RapidIO Technical Working Group, “RapidIO Physical Layer 8/16 LP-LVDS AC Specification,” pp. IV-95 –IV-108, Mar. 2001.
Semiconductor Industry Association, “SEMI Draft Documents #2928-Specification for Overall Digital Timing Accuracy,” pp. 3–5, 1999.
C. Stanghan and B. MacDonald, “Electrical Characterization of Packages for High-Speed Integrated Circuits,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 8. no. 4, pp. 468–473, 1985.
B. Wang, Y.B. Cho, S. Tabatabaei, and A. Ivanov, “Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-offs for High-Speed Interconnect Device Testing,” in Proc. IEEE Twelfth Asian Test Symposium (ATS'2003), 2003, pp. 348–353.
D. Wimmers, K. Sakaitani, and B. West, “500 MHz Testing on a 100 MHz Tester,” in Proceedings of IEEE International Test Conference, 1994, pp. 273–278.
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Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada.
During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada.
He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements.
Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications.
Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control.
André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia.
His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs.
Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia.
Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992.
He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC.
Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic.
His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.
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Wang, B., Kuo, A., Farahmand, T. et al. A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. J Electron Test 21, 621–630 (2005). https://doi.org/10.1007/s10836-005-4819-4
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DOI: https://doi.org/10.1007/s10836-005-4819-4