Abstract
This paper reports an efficient BIST solution for VLSI circuits. The solution is based on an on-chip Pseudo-Random Pattern Generator (PRPG) for the CUTs (Circuit Under Test) of a VLSI chip that may be accessed through a full or partial scan path. The test solution guarantees non-issuance of the test patterns declared prohibited to a CUT. An n-bit Test Pattern Generator (TPG), for any arbitrary value of n, has been designed in linear time around the nonlinear Cellular Automata (CA). Experimental results confirm the enhanced pseudo-random quality of the generated test patterns, avoiding prohibited patterns due to application of nonlinear CA.
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Das, S., Kundu, A., Sikdar, B.K. et al. Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. J Electron Test 21, 95–107 (2005). https://doi.org/10.1007/s10836-005-5290-y
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DOI: https://doi.org/10.1007/s10836-005-5290-y