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Selection of Crosstalk-Induced Faults in Enhanced Delay Test

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Abstract

Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. In this paper, we address the problem of enhanced delay test considering crosstalk-induced effects. Two types of crosstalk-induced delay fault model in related works are analyzed according to their relationship to common delay fault models. The difficulties in test generation using these fault models are shown. Based on the discussion, a single precise crosstalk-induced path delay fault model, S-PCPDF model, is proposed for circuits given delay assignment. A target S-PCPDF fault gives information on a sub-path to be sensitized to generate necessary transitions coupled to a critical path. It is then convenient to enhance conventional path delay fault ATPG algorithms to implement ATPG systems for crosstalk-induced path delay faults by adding the constraints on the sub-path. We then propose two approaches to reducing the number of target S-PCPDF faults. One is based on constraints for side-inputs of paths under test. The other is based on pre-specified states during test generation for the critical path. Experimental results on ISCAS’89 benchmark circuits showed that the proposed approaches can reduce the number of target faults significantly and efficiently. The CPU time for fault list reduction and test pattern generation is acceptable for circuits of reasonable sizes.

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Authors and Affiliations

  1. Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China

    Huawei Li & Xiaowei Li

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  1. Huawei Li
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  2. Xiaowei Li
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Correspondence to Huawei Li.

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Huawei Li received her B.S. degree in computer science from Xiangtan University in 1996, and M.S. and Ph.D. degrees from the Institute of Computing Technology, Chinese Academy of Sciences in 1999 and 2001 respectively. She is now an associate professor at the Institute of Computing Technology, Chinese Academy of Sciences. Her research interests include VLSI/SoC design verification and test generation, delay test, and dependable computing.

Xiaowei Li received his B.Eng. and M.Eng. degrees in computer science from Hefei University of Technology (China) in 1985 and 1988 respectively, and his Ph.D. degree in computer science from the Institute of Computing Technology, Chinese Academy of Sciences in 1991. Dr. Li joined Peking University (China) as a Postdoctoral Research Associate in 1991, and was promoted to Associate Professor in 1993, all with the Department of Computer Science and Technology. From 1997 to 1998, he was a Visiting Research Fellow in the Department of Electrical and Electronic Engineering at the University of Hong Kong. In 1999 and 2000, he was a Visiting Professor in the Graduate School of Information Science, Nara Institute of Science and Technology, Japan. He Joined the Institute of Computing Technology, Chinese Academy of Sciences as a professor in 2000. At present, he is a vice-director of the laboratory of information networks. His research interests include VLSI/SoC design verification and test generation, design for testability, low-power design, dependable computing. Dr. Li received the Natural Science Award from the Chinese Academy of Sciences in 1992, the Certificate of Appreciation from IEEE Computer Society in 2001. He is a senior member of IEEE and a senior member of China Computer Federation. He is an editor of Journal of Computer Science and Technology and Journal of Computer-Aided Design & Computer Graphics (in Chinese).

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Li, H., Li, X. Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J Electron Test 21, 181–195 (2005). https://doi.org/10.1007/s10836-005-6147-0

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  • DOI: https://doi.org/10.1007/s10836-005-6147-0

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