Abstract
The long and complex procedure to test ADCs constitutes an important issue in the context of mixed-signal testing. To lower the testing costs, we propose shorter but less selective test flows solely based on spectral analysis. This paper investigates the efficiency that can be achieved using this approach and studies the influence of the ADC specifications on the efficiency of the proposed dynamic-only test flows.
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References
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Florence Azaïs received the Ph.D. degree in electrical engineering from the University of Montpellier, France in 1996. She is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as a researcher of the National Council of Scientific Research (CNRS). Since 1993, she has been interested in the general domain of test and reliability of integrated circuits and systems. Her main research interests include fault modeling, analog and mixed-signal circuit testing, MEMS testing, reliability and failure analysis of integrated systems. She has authored or co-authored over 80 international papers on these topics. She also served as a member of the Program Committee of several international conferences (DATE, ICCD, ETS, IMSTW, LATW).
Serge Bernard received the M.S. degree in Electrical Engineering from the University of Paris XI, France in 1998 and the Ph.D. degree in Electrical Engineering from the University of Montpellier, France in 2001. He is a researcher of the National Council of Scientific Research (CNRS) in the Microelectronics Department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM). His main research interests include Test, Design-For-Testability and Built-In-Self-Test for mixed-signal circuits and Design-For-Reliability for medical application ICs.
Yves Bertrand is a Professor at the University of Montpellier (France). He works at the Microelectronics Department of the Laboratoire d’Automatique, Robotique et Microélectronique de Montpellier (LIRMM). Previously, Yves Bertrand worked in the field of solid-state physics and published several papers, especially on the photoemission of the semiconductors under synchrotron radiation. He joins the LIRMM in 1988. His research interests are principally, Fault Modeling, Design-For-Test and Built-In Self-Test for digital and mixed-signal analog/digital Integrated Circuits. He is author or co-author of about 200 papers in the field of solid-state physics and microelectronics. He is presently responsible for the CRTC (Centre de Ressources de Test du CNFM), which is the Common Test Resources Center for the French and European Universities.
Mariane Comte took her Master of Engineering and Master of Sciences degrees in microelectronics engineering at INPG, (Institut National Polytechnique de Grenoble, National Engineering University Institution of Grenoble), France, in 2000. She carried out her Ph.D. studies at LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier, Computer Sciences, Robotics and Microelectronics Laboratory of Montpellier), France, working on Analog-to-Digital Converter testing, and received Ph.D. degree in microelectronics from the University of Montpellier, France, in 2003. After a post-doctoral fellow position at the Computer Design and Test Laboratory of NAIST (Nara Institute of Science and Technology), Japan, where she investigated on the detection of Gate-Oxide Shorts in Domino Logic cells, she is currently working as an assistant professor at the University of Montpellier. Her fields of interest spread from analog and mixed-signal testing to defect modeling.
Michel Renovell is head of the Microelectronics Department at LIRMM (Laboratory of Computer Science, Automation and Microelectronics of Montpellier). His research interests include: Fault modeling, Analog testing and FPGA testing. He is Vice-Chair of the IEEE TTTC (Test Technology Technical Committee). He is a member of the editorial board of JETTA and the editorial board of IEEE Design & Test. Michel has been General Chair of the International Mixed Signal Testing Workshop IMSTW2000, the Field Programmable Logic Conference FPL2002 and the European Test Symposium ETS2004.
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Azaïs, F., Bernard, S., Bertrand, Y. et al. Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J Electron Test 21, 291–298 (2005). https://doi.org/10.1007/s10836-005-6358-4
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DOI: https://doi.org/10.1007/s10836-005-6358-4