Skip to main content
SpringerLink
Log in

Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The viability of magnetically detecting open faults among multiple power and ground pins of an integrated-circuit package is investigated. The experimental technique is based on injecting current to the leadframe through the chip, and individually sensing the lateral magnetic field of each VDD or GND lead on top of the package. Field distribution in sensor plane is analyzed in order to determine the interference conditions under which correct classification of pin continuity is possible. It is shown that field-based classification benefits from a mildly subtractive interference. Also proposed is a model-based algorithm by which lead currents are calculated from field readings. Classification on the basis of current is shown to be robust against interference. Predictions are verified with experimentation conducted on a PQFP package with a moving Hall sensor.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. T.S. Aytur, T. Ishikawa, and B.E. Boser, “A 2.2-mm2 CMOS Bioassay Chip and Wireless Interface,” in Symp. on VLSI Circuits Dig. Tech. Papers, Berkeley, CA, USA, 2004, pp. 314–317.

  2. S. Chatraphorn, E.F. Fleet, F.C. Wellstood, and L.A. Knauss, “Noise and Spatial Resolution in SQUID Microscopy,” IEEE Trans. Appl. Supercond., vol. 11, pp. 234–237, 2001.

    Article  Google Scholar 

  3. U. Çilingiroğlu, “Backdrive Damage Mechanisms in Modern Integrated Circuits,” http://www.home.agilent.com/upload/cmc_upload/All/Safeguard_2005.pdf.

  4. O. Crépel, P. Poirier, P. Descamps, R. Desplats, P. Perdu, G. Haller, and A. Firiti, “Magnetic Microscopy for ICs Failure Analysis: Comparative Case Studies Using SQUID, GMR and MTJ Systems,” in Proc. International Symposium on the Physical and Failure Analysis of Integrated Circuits, Taiwan, 2004, pp. 45–48.

  5. F. de Jong, B. Kup, and R. Schuttert, “Power Pin Testing: Making the Test Coverage Complete,” in Proc. International Test Conference, Atlantic City, NJ, USA, 2000, pp. 575–584.

  6. C. Dolabdjian, A. Qasimi, and C. Cordier, “Applied Magnetic Sensing: A Long Way,” in IEEE International Conference on Sensors, 2003, pp. 477–482.

  7. E.F. Fleet, S. Chatraphorn, F.C. Wellstood, and L.A. Knauss, “HTS Scanning SQUID Microscopy of Active Circuits,” IEEE Trans. Appl. Supercond., vol. 9, pp. 4103–4106, 1999.

    Article  Google Scholar 

  8. P.N. King, D.T. Crook, and J.E. McDermid, Multiple Axis Magnetic Test for Open Integrated Circuit Pins, US Patent 6,529,019, March 2003.

  9. J.A. Kirtley and J.P. Wikswo Jr., “Scanning SQUID Microscopy,” Annu. Rev. Mater. Sci., vol. 2, pp. 117–148, 1999.

    Article  Google Scholar 

  10. M.A. Laing and R.J. Williams, Method of Testing Continuity of a Connection Between an Integrated Circuit and a Printed Circuit Board by Current Probing Integrated Circuit, US Patent 5,399,975, March 1995.

  11. H. Manhaeve and S. Kerckenaere, “An On-chip Detection Circuit for the Verification of IC Supply Connections,” in Proc. IEEE International Symposium on Defect and fault Tolerance in VLSI Systems, San Francisco, CA, USA, 2001, pp. 57–65.

  12. K.P. Parker and J.E. McDermid, Integrated or Intrapackage Capability for Testing Electrical Continuity between an Integrated Circuit and other Circuitry, US Patent 6,087,842, July 2000.

  13. K.P. Parker and J.E. McDermid, Integrated or Intrapackage Capability for Testing Electrical Continuity between an Integrated Circuit and other Circuitry, US Patent 6,097,203, August 2000.

  14. B.D. Schrag, X.Y. Liu, M.J. Carter, and G. Xiao, “Scanning Magnetoresistive Microscopy for Die-level Sub-micron Current Density Mapping,” in Proc. International Symp. for Testing anf Failure Analysis, Fall River, MA, 2003, pp. 2–5.

  15. M.M.V. Tegethoff, K.P. Parker, and K. Lee, “Opens Board Test Coverage: When is 99% really 40%?” in Proc. International Test Conference, Washington, DC, USA, 1996, pp. 333–339.

  16. D. van de Lagemaat,“Testing Multiple Power Connections with Boundary Scan,” in Proc. European Test Conference, Paris, France, 1989, pp.127–130.

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Yeditepe University, 26 Ağustos Yerleşimi, 34755, Kayışdağı-İstanbul, Turkey

    Uğur Çilingiroğlu

Authors
  1. Uğur Çilingiroğlu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Uğur Çilingiroğlu.

Additional information

Editor: M. Sachdev

This work was partially funded by Agilent Technologies. The author was formerly with Electrical Engineering Department, Texas A&M University, College Station, TX 77843, USA.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Çilingiroğlu, U. Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults. J Electron Test 23, 25–34 (2007). https://doi.org/10.1007/s10836-006-0508-1

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-006-0508-1

Keywords

Search

Navigation