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Defect-tolerant Logic with Nanoscale Crossbar Circuits

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Abstract

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.

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Authors and Affiliations

  1. HP Labs, 1501 Page Mill Road, Palo Alto, CA, USA

    Tad Hogg & Greg Snider

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  1. Tad Hogg
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  2. Greg Snider
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Correspondence to Tad Hogg.

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Editor: M. Tehranipoor

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Hogg, T., Snider, G. Defect-tolerant Logic with Nanoscale Crossbar Circuits. J Electron Test 23, 117–129 (2007). https://doi.org/10.1007/s10836-006-0547-7

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  • DOI: https://doi.org/10.1007/s10836-006-0547-7

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