Abstract
Simulation is still the primary verification method for integrated circuit designs, and coverage evaluation is indispensable for it on account of its incompleteness. As the functional complexity of modern designs is increasing dramatically, it is necessary to take observability into consideration for coverage metrics. In this paper we extend factored use-definition chains (FUD chains), a mature data structure in compilers, from sequential software to concurrent hardware design, and propose dynamic FUD chains (DFUD chains). Based on it, we present an observability model and an algorithm to evaluate observability-based statement coverage. This technique has several advantages. Firstly, it could be easily integrated into compilers or simulators for hardware description languages, since it utilizes many flow analysis techniques adopted in compilers. Secondly, it can be combined with many controllability metrics, such as statement coverage metric, since the observability model is based on definitions and uses of variables. The proposed technique has been implemented as a prototype tool for Verilog designs, and experimental results show its benefits.
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*This paper is the revised version of “An efficient observability evaluation algorithm based on factored use-def chains” in the Proceedings of IEEE Asian Test Symposium, 2003.
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Lv, T., Fan, JP., Li, XW. et al. Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. J Electron Test 22, 273–285 (2006). https://doi.org/10.1007/s10836-006-8634-3
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DOI: https://doi.org/10.1007/s10836-006-8634-3