Abstract
Testing integrated circuits (ICs) is understood as the task of filtering out defective ICs that violate data sheet specifications. The costs of this filter comprise both the direct cost of testing a device and the indirect cost of test escapes and test yield–loss. For analog and mixed-signal devices, such as data converters, traditional methods of estimating the defect and test escape levels require large sample sets of devices. This is because the defect level induced by manufacturing process variations is typically low. In this work, a model-based method of estimating defect and test escape levels is described. For this method, a small set of sample devices is sufficient, as we first derive a manufacturing process model which is then used to simulate the manufacturing of a large number of devices. These simulation results are subsequently used for the purposes of estimating the defect and test escape levels, as well as the test-related yield–loss when applying a given test. With these estimates, the quality and indirect costs of a test can be determined as a function of the test limits and guard-bands applied in production test.
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Wegener, C., Kennedy, M.P. Test Development Through Defect and Test Escape Level Estimation for Data Converters. J Electron Test 22, 313–324 (2006). https://doi.org/10.1007/s10836-006-9457-y
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DOI: https://doi.org/10.1007/s10836-006-9457-y