Abstract
The design of secure ICs requires fulfilling means conforming to many design rules in order to protect access to secret data. On the other hand, designers of secure chips cannot neglect the testability of their chip since high quality production testing is primordial to a good level of security. However, security requirements may be in conflict with test needs and testability improvement techniques that increase both observability and controllability. In this paper, we propose to merge security and testability requirements in a control-oriented design for security scan technique. The proposed security scan design methodology induces an adaptation of two main aspects of testability technique design: protection at protocol level and at scan path level. Without loss of generality, the proposed solution is evaluated on a simple crypto chip in terms of security and design cost.
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Hély, D., Bancel, F., Flottes, ML. et al. Securing Scan Control in Crypto Chips. J Electron Test 23, 457–464 (2007). https://doi.org/10.1007/s10836-007-5000-z
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DOI: https://doi.org/10.1007/s10836-007-5000-z