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Performance-Optimized Design for Parametric Reliability

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Abstract

Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations (Bowman et al., IEEE J Solid State Circuits 37:183–190, 2002), making it a significant problem for design and manufacture of DSM ICs. Adaptive design techniques are fast evolving as a potential solution to this problem. Such techniques facilitate reconfiguration of an IC to enable its operation across process corners, thus ensuring parametric reliability in such ICs, and also improving manufacturing yield. In this paper, adaptive design techniques with a focus on timing of ICs, i.e., performance-optimized adaptive design, are explored. The focus of such performance-optimized adaptive design techniques is to ensure that adaptation does not cause an IC to violate timing specifications, thus giving priority to performance, which remains one of the most important parameters of an IC.

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Acknowledgment

The authors would like to thank Antony Sebastine and Whitney J. Townsend for design of the multipliers.

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Authors and Affiliations

  1. Computer Engineering Research Center, The University of Texas at Austin, 201 E 24th Street, Ace 6. 134, Austin, TX, 78705, USA

    Ramyanshu Datta & Jacob A. Abraham

  2. Vivante Corporation, Santa Clara, CA, USA

    Abdulkadir Utku Diril

  3. Georgia Institute of Technology, Atlanta, GA, USA

    Abhijit Chatterjee

  4. IBM Austin Research Laboratory, Austin, TX, USA

    Kevin J. Nowka

Authors
  1. Ramyanshu Datta
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  2. Jacob A. Abraham
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  3. Abdulkadir Utku Diril
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  4. Abhijit Chatterjee
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  5. Kevin J. Nowka
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Corresponding author

Correspondence to Ramyanshu Datta.

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Responsible Editor: N. A. Touba

This work was supported in part by the IBM Faculty Partnership Award Program, and in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation(MARCO).

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Datta, R., Abraham, J.A., Utku Diril, A. et al. Performance-Optimized Design for Parametric Reliability. J Electron Test 24, 129–141 (2008). https://doi.org/10.1007/s10836-007-5001-y

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  • DOI: https://doi.org/10.1007/s10836-007-5001-y

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