Abstract
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of overtesting in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between overtesting prevention and test compression.





Similar content being viewed by others
Notes
Parts of the article have been presented at the Design Automation and Test in Europe (DATE) Conference 2006.
References
Bryant R (1986) Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. 35(8):677–691
Dervisoglu B, Stong G (1991) Design for testability: using scanpath techniques for path-delay test and measurement. In: Int’l test conf., pp 365–374
Engelke P, Polian I, Renovell M, Seshadri B, Becker B (2004) The pros and cons of very-low-voltage testing: an analysis based on resistive short defects. In: VLSI test symp., pp 171–178
Fudoli A, Ascagni A, Appello D, Manhaeve H (2003) A practical evaluation of IDDQ test strategies for deep submicron production test application. experiences and targets from the field. In: European test workshop., pp 65–70
Giles G, Irby J, Toneva D, Tsai K-H (2005) Built-in constraint resolution. In: Int’l test conf.
Hao H, McCluskey E (1991) Resistive shorts within CMOS gates. In: Int’l test conf., pp 292–301
Henftling M, Wittmann H (1995) Bit parallel test pattern generation for path delay faults. In: European design and test conf., pp 521–525
Krstić A, Liou J-J, Cheng K-T, Wang L-C (2003) On structural vs. functional testing for delay faults. In: Int’l symp. on quality electronic design, pp 438–441
Lin Y-C, Lu F, Cheng K-T (2005a) Pseudo-functional scan-based BIST for delay fault. In: VLSI test symp., pp 229–234
Lin Y-C, Lu F, Yang K, Cheng K-T (2005b) Constraint extraction for pseudo-functional scan-based delay testing. In: Asia and South Pacific design autom. conf., pp 166–171
Liu X, Hsiao M (2003) Constrained ATPG for broadside transition testing. In: Int’l symp. on defect and fault tolerance in VLSI systems, pp 175–184
Liu X, Hsiao M (2005) A novel transition fault ATPG that reduces yield loss. IEEE Des. Test Comput. 22(6):576–584
Madge R, Benware B, Daasch W (2003) Obtaining high defect coverage for frequency-dependent defects in complex ASICs. IEEE Des. Test Comput. 20(5): 46–53
Mitra S, Avra L, McCluskey E (1997) Scan synthesis for one-hot signals. In: Int’l test conf., pp 414–422
Pecht M, Radojic R, Rao G (1998) Managing silicon chip reliability. CRC Press.
Pomeranz I (2004) On the generation of scan-based test sets with reachable states for testing under functional operation conditions. In: Design autom. conf., pp 928–933
Rajski J, Tyszer J, Kassab M, Mukherjee, N (2004) Embedded deterministic test. IEEE Trans. CAD 23(5):776–792
Rearick J (2001) Too much delay fault coverage is a bad thing. In: Int’l test conf., pp 624–633
Savir J (1994) Broad-Side delay test. IEEE Trans. CAD 13(8):1057–1064
Saxena J, Butler K, Jayaram V, Kundu S, Arvind N, Sreeprakash P, Hachinger M (2003) A case study of IR-drop in structured at-speed testing. In: Int’l test conf., pp 1098–1104
Tafertshofer P, Ganz A, Henftling M (1997) A SAT-based implication engine for efficient ATPG, equivalence checking, and optimization of netlists. In: Int’l Conf. on CAD, pp 648–655
Tehranipour M, Nourani M, Chakrabarty, K (2004) Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression. In: Design, automation and test in Europe, pp 173–178.
Vedula V, Abraham J (2000) A novel methodology for hierarchical test generation using functional constraint composition. In: Int’l high-level validation and test workshop, pp 9–14
Acknowledgements
This work was supported in part by 21st Century COE (Center of Excellence) Program “Ubiquitous Networked Media Computing” and in part by JSPS (Japan Society for the Promotion of Science) under Grants-in-Aid for Scientific Research B(2)(No. 15300018). We are thankful to Prof. Sudhakar M. Reddy for fruitful discussions on overtesting.
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: A. Parekhji
Rights and permissions
About this article
Cite this article
Polian, I., Fujiwara, H. Functional Constraints vs. Test Compression in Scan-Based Delay Testing. J Electron Test 23, 445–455 (2007). https://doi.org/10.1007/s10836-007-5013-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-007-5013-7