Abstract
In the recent years both software and hardware techniques have been adopted to carry out reliable designs, aimed at autonomously detecting the occurrence of faults, to allow discarding erroneous data and possibly performing the recovery of the system. The aim of this paper is the introduction of a combined use of software and hardware approaches to achieve a complete fault coverage in generic IP processors, with respect to SEU faults. Software techniques are preferably adopted to reduce the necessity and costs of modifying the processor architecture; since a complete fault coverage cannot be achieved, partial hardware redundancy techniques are then introduced to deal with the remaining, not covered, faults. The paper presents the methodological approach adopted to achieve the complete fault coverage, the proposed resulting architecture, and the experimental results gathered from the analysis of the fault injection campaigns.
Similar content being viewed by others
References
Alkhalifa Z, Nair VSS, Krishnamurthy N, Abraham JA (1999) Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans Parallel Distrib Syst 10(6):627–641
Bernardi P, Bolzani L, Rebaudengo M, Sonza Reorda M, Violante M (2005) An integrated approach for increasing the soft-error detection capabilities in SoCs processors. In Proc. 20th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 445–453
Bolchini C, Miele A, Pomante L, Salice F, Sciuto D (2004) Reliable system co-design: the FIR case study. In Proc. 19th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Cannes, France, pp 433–441
Bolchini C, Miele A, Salice F, Sciuto D (2005) A model of soft error effects in generic IP processors. In Proc. 20th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 334–342
Bolchini C, Pomante L, Salice F, Sciuto D (2005) Reliable system specification for self-checking data-paths. In Proc. of the Conf. on Design, Automation and Test in Europe. IEEE Computer Society, Washington, DC, USA, pp 1278–1283
Bolchini C, Miele A, Rebaudengo M, Sterpone L, Violante M, Sciuto D (2006) Combined software and hardware techniques for the design of reliable IP processors. In Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 265–273
Civera P, Macchiarulo L, Rebaudengo M, Sonza Reorda M, Violante M (2002) An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits. Journal of Electronic Testing: Theory and Applications 18(3):261–271, June
Dodd PE, Massengill LW (2003) Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602, June
Gaisler J (2003) The LEON2 IEEE-1754 (SPARC V8) Processor http://www.gaisler.com
Goloubeva O, Rebaudengo M, Reorda MS, Violante M (2005) Improved software-based processor control-flow errors detection technique. In Reliability and Maintainability Symposium, 2005. Proceedings. Annual, pp 583–589
Rebaudengo M, Sonza Reorda M, Torchiano M, Violante M (1999) Soft-error detection through software fault-tolerance techniques. In Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 210–218
Rebaudengo M, Sonza Reorda M, Violante M, Nicolescu B, Velazco R (2002) Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparative study. IEEE Trans Nucl Sci (49)3:1491–1495, June
Ziegler F et al (1996) Terrestrial cosmic rays and soft errors. IBM J Res Develop 40(1)
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: N. A. Touba
Rights and permissions
About this article
Cite this article
Bolchini, C., Miele, A., Rebaudengo, M. et al. Software and Hardware Techniques for SEU Detection in IP Processors. J Electron Test 24, 35–44 (2008). https://doi.org/10.1007/s10836-007-5028-0
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-007-5028-0