Skip to main content
Log in

Fast PWM-Based Test for High Resolution ΣΔ ADCs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADCs. Simulations and measurements showed a discrimination threshold on specification parameters up to −90 dBc. The proposed method helps to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. International Technology Roadmap for Semiconductors (2003) available online: http://public.itrs.net

  2. Provost B, Sanchez-Sinecio E (2003) On-chip ramp generators for mixed-signal BIST and ADC self-test. IEEE J Solid-State Circuits 38(2):263–273 (Feb)

    Article  Google Scholar 

  3. Kuyel T (1999) Linearity testing issues of analog-to-digital converters. In: Proceedings of the International Test Conference 1999, pp 747–756 (Sept)

  4. Frisch A, Almy T (1997) HABIST: histogram-based analog built in self test, IEEE International Test Conference, ITC97, 3–5th Nov. Washington, DC, USA, pp 760–767

  5. Toner M, Roberts G (1993) A BIST scheme for an SNR test of a Sigma Delta ADC. In: International Test Conference, Baltimore, MD, October 1993, pp. 805-814

  6. Ohletz MJ (1991) Hybrid built in self-test (HBIST) for mixed analogue/digital ICs. 2nd European Test Conference, ETC91, 10–12th April. Munich, Germany, pp 307–316

  7. Teraoka E, Kengaku T, Yasui I, Ishikawa K, Matsuo T, Wakada H (1997) Built-in self-test for ADC and DAC in a single-chip speech CODEC. In: IEICE Transactions on Fundamentals of Electronics Communications E80A(2):339–345

    Google Scholar 

  8. Sunter SK, Nagi N (1997) A simplified polynomial-fitting algorithm for DAC and ADC BIST. In: IEEE International Test Conference, ITC97, Washington, DC, USA, 3–5th Nov. pp 389–395

  9. Roy A, Sunter S, Fudoli A, Appello D (2002) High accuracy stimulus generation for ADC BIST. In: IEEE International Test Conference, ITC02, Baltimore, MD, USA, 8–10th Oct., pp 1031–1039

  10. De Venuto D, Marchione G, Reyneri L (2005) A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC. In: Proceedings of IEEE International Symp. on Quality Design (ISQED 05), San Josè, CA (21–23 March)

  11. De Venuto D, Dell’Olio F, Reyneri L (2005) Optimization of FPGA-based test strategy for high resolution ADC. In: Proceedings of IEEE International Mixed Signal Workshop (IMSTW05), Cannes, France (June)

  12. De Venuto D, Reyneri L (2006) ADC test technique. Patent n./064092

  13. Aziz PM, Sorensen HV, Van Der Spiegel J (1996) An overview of sigma-delta converters. IEEE Sig Process Mag 13:61–84 (Jan)

    Article  Google Scholar 

  14. Reyneri LM, Renga F (2004) Speeding-up the design of HW/SW implementations of neuro-fuzzy systems using the codesimulink environment. In: Applied Soft Computing (April)

  15. http://polimage.polito.it/groups/codesimulink.it

Download references

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Daniela De Venuto or Leonardo Reyneri.

Additional information

Responsible Editor: M. Lubaszewski

Rights and permissions

Reprints and permissions

About this article

Cite this article

De Venuto, D., Reyneri, L. Fast PWM-Based Test for High Resolution ΣΔ ADCs. J Electron Test 23, 539–548 (2007). https://doi.org/10.1007/s10836-007-5047-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-007-5047-x

Keywords

Navigation