Abstract
This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution ΣΔ ADCs. Simulations and measurements showed a discrimination threshold on specification parameters up to −90 dBc. The proposed method helps to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.
Similar content being viewed by others
References
International Technology Roadmap for Semiconductors (2003) available online: http://public.itrs.net
Provost B, Sanchez-Sinecio E (2003) On-chip ramp generators for mixed-signal BIST and ADC self-test. IEEE J Solid-State Circuits 38(2):263–273 (Feb)
Kuyel T (1999) Linearity testing issues of analog-to-digital converters. In: Proceedings of the International Test Conference 1999, pp 747–756 (Sept)
Frisch A, Almy T (1997) HABIST: histogram-based analog built in self test, IEEE International Test Conference, ITC97, 3–5th Nov. Washington, DC, USA, pp 760–767
Toner M, Roberts G (1993) A BIST scheme for an SNR test of a Sigma Delta ADC. In: International Test Conference, Baltimore, MD, October 1993, pp. 805-814
Ohletz MJ (1991) Hybrid built in self-test (HBIST) for mixed analogue/digital ICs. 2nd European Test Conference, ETC91, 10–12th April. Munich, Germany, pp 307–316
Teraoka E, Kengaku T, Yasui I, Ishikawa K, Matsuo T, Wakada H (1997) Built-in self-test for ADC and DAC in a single-chip speech CODEC. In: IEICE Transactions on Fundamentals of Electronics Communications E80A(2):339–345
Sunter SK, Nagi N (1997) A simplified polynomial-fitting algorithm for DAC and ADC BIST. In: IEEE International Test Conference, ITC97, Washington, DC, USA, 3–5th Nov. pp 389–395
Roy A, Sunter S, Fudoli A, Appello D (2002) High accuracy stimulus generation for ADC BIST. In: IEEE International Test Conference, ITC02, Baltimore, MD, USA, 8–10th Oct., pp 1031–1039
De Venuto D, Marchione G, Reyneri L (2005) A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC. In: Proceedings of IEEE International Symp. on Quality Design (ISQED 05), San Josè, CA (21–23 March)
De Venuto D, Dell’Olio F, Reyneri L (2005) Optimization of FPGA-based test strategy for high resolution ADC. In: Proceedings of IEEE International Mixed Signal Workshop (IMSTW05), Cannes, France (June)
De Venuto D, Reyneri L (2006) ADC test technique. Patent n./064092
Aziz PM, Sorensen HV, Van Der Spiegel J (1996) An overview of sigma-delta converters. IEEE Sig Process Mag 13:61–84 (Jan)
Reyneri LM, Renga F (2004) Speeding-up the design of HW/SW implementations of neuro-fuzzy systems using the codesimulink environment. In: Applied Soft Computing (April)
Author information
Authors and Affiliations
Corresponding authors
Additional information
Responsible Editor: M. Lubaszewski
Rights and permissions
About this article
Cite this article
De Venuto, D., Reyneri, L. Fast PWM-Based Test for High Resolution ΣΔ ADCs. J Electron Test 23, 539–548 (2007). https://doi.org/10.1007/s10836-007-5047-x
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-007-5047-x