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On Composite Leakage Current Maximization

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Abstract

Sub-threshold, gate and reverse biased junction band-to-band tunneling leakage currents depend on the logic inputs of a CMOS circuit. In this paper, we consider all leakage currents together and generate pattern with the objective of maximizing the overall leakage current to avoid any optimism in leakage current estimation. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We propose a heuristic with reduced complexity by looking for a lower and an upper bound instead. The bounds tighten progressively with computation and converge asymptotically on a provably exact solution. By appropriately setting the objective function, the same algorithm may also be applied to find the pattern that minimizes the leakage power in the system idle state, which is considered to be ∼50% of the total power consumed in the current technology generations.

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References

  1. Aloul FA, Hassoun S, Sakallah KA, Blaauw D (2002) Robust SAT-based search algorithm for leakage power reduction. In: Proc Power and Timing Modeling, Optimization and Simulation (PATMOS), pp 167–177

  2. ASIC Standard Cell Library Design by Graham Petley, http://www.vlsitechnology.org

  3. Bobba S, Hajj IN (1999) Maximum leakage power estimation for CMOS circuits. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pp 116–124

  4. Brown R, Burns J, Devgan A (2003) Efficient techniques for gate leakage estimation. International Symposium on Low Power Electronics and Design (ISLPED), Proceedings, pp 100–103

  5. Cao Y, Orhansky M, Sato T, Sylvester D, Hu C et al (2003) Spice up your MOSFET Modeling. IEEE Circuits Devices Mag 19(4):17–23

    Article  Google Scholar 

  6. Chai D, Kuehlmann A (2004) Circuit-based Preprocessing of ILP and its applications in leakage minimization and power estimation. In: Proc IEEE Intl Conf Computer Design (ICCD), pp 387–392

  7. Chopra K, Vrudhula SBK (2004) Implicit pseudo boolean enumeration algorithms for input vector control. In: Proc 41st ACM/IEEE Design Automation Conference, pp 767–772

  8. De V, Borkar S (1999) Technology and design challenges for low power & high performance. In: IEEE Int Symp Low Power Electronics Design, pp 163–168

  9. Devadas S, Keutzer K, White J (1992) Estimation of power dissipation in CMOS combinational circuits using boolean function manipulation. IEEE Trans Comput-Aided Des 11(3):373–383, Mar

    Article  Google Scholar 

  10. Devadas S, Keutzer K, Malik S (1993) Computation of floating mode delay in combinational circuits: theory and algorithms. IEEE Trans Comput-Aided Des 12(12):1913–1923, Dec

    Article  Google Scholar 

  11. Devadas S, Keutzer K, Malik S, Wang A (1993) Computation of floating mode delay in combinational circuits: practice and implementation. IEEE Trans Comput-Aided Des 12(12):1924–1934, Dec

    Article  Google Scholar 

  12. Ferré A, Figueras J (1996) On estimating bounds of the quiescent current for IDDQ testing. In: Proc. 14th VLSI Test Symp, pp 106–111

  13. Ferre A, Figueras J (2002) Leakage power bounds in CMOS digital technologies. IEEE Trans Comput-Aided Des 21:731–738, June

    Article  Google Scholar 

  14. Garey MR, Johnson DS (1979) Computers and intractability: a guide to the theory of NP-completeness. W. H. Freeman, New York

    MATH  Google Scholar 

  15. Gu RX, Elmasry MI (1996) Power dissipation analysis and optimization of deep submicron CMOS digital circuits. IEEE J Solid-State Circuits 31:707–713, May

    Article  Google Scholar 

  16. Halter P, Najm FN (1997) A gate-level leakage power reduction method for ultra-low-power CMOS circuits. In: IEEE Custom Integrated Circuits Conf, pp 475–478

  17. Hu C et al (2000) BSIM4 gate leakage model including source–drain partition. International Electron Device Meeting, pp 815–818

  18. Hu C et al (2004) BSIM4.5.0 Mosfet Model, User’s Manual

  19. Johnson MC, Somasekhar D, Roy K (1999) Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans Comput-Aided Des 18:714–725, June

    Article  Google Scholar 

  20. Kriplani, Najm, Hajj (1995) Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution. IEEE Trans Comput-Aided Des Integr Circuits Syst 14(8):998–1012, Aug

    Article  Google Scholar 

  21. Kundu S, Mak TM, Galivanche R (2004) Trends in manufacturing test methods and their implications. International Test Conference, pp 679–687

  22. Larrabee T (1992) Test pattern generation using boolean satisfiability. IEEE Trans Comput-Aided Des 11(1):4–15, Jan

    Article  Google Scholar 

  23. Lee D, Blaauw D, Sylvester D, Gate oxide leakage current analysis and reduction for VLSI circuits. Very Large Scale Integration (VLSI) Systems. IEEE Transactions on 12(2):155–166

  24. Lee D, Kwong W, Blaauw D, Sylvester D, Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in Nanometer CMOS Design. ISQED ′03, Proceedings on, pp 287–292

  25. Malik S, Mahajan Y, Fu Z, Chaff Z (2004) An efficient SAT solver, theory and applications of satisfiability testing, selected revised papers series: lecture notes in computer science

  26. Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S (2001) Chaff: engineering an efficient SAT Solver. In: Proc. Design Automation Conference (DAC), pp 530–535

  27. Mukhopadhyay S, Bhunia S, Roy K (2005) Modeling and analysis of loading effect in leakage of nano-scaled bulk-CMOS logic circuits. DATE, Proceedings, pp 1:224–229

  28. Yang S, Wolf W,x Vijaykrishnan W, Xie Y, Wang W (2005) Accurate stacking effect macro-modeling of leakage power in Sub-100 nm circuits. VLSI Design, International Conference on, pp 165–170

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Authors and Affiliations

  1. Department of Electrical & Computer Engineering, University of Massachusetts, Amherst, MA, USA

    Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal & Sandip Kundu

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  1. Ashesh Rastogi
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  2. Kunal P. Ganeshpure
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  3. Alodeep Sanyal
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  4. Sandip Kundu
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Correspondence to Sandip Kundu.

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Responsible Editor: N. Nicolici

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Rastogi, A., Ganeshpure, K.P., Sanyal, A. et al. On Composite Leakage Current Maximization. J Electron Test 24, 405–420 (2008). https://doi.org/10.1007/s10836-007-5049-8

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  • DOI: https://doi.org/10.1007/s10836-007-5049-8

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