Skip to main content
SpringerLink
Log in

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The concept of model-based test was developed in order to reduce the production test effort for data converters (Cherubal and Chatterjee (IEEE Trans Circuits Syst part I 50(3):317–327, 2003); Stenbakken and Souders (1985) Modelling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817; Wegener and Kennedy (IEEE Trans Circuits Syst I 51(1):213–217, 2004); Wrixon and Kennedy (IEEE Trans Instrum Meas IM-48(5):978–985, 1999)). In applying this concept, a vector of model parameters is determined for each device under test (DUT). Typically, this model parameter vector is merely used to calculate the DUT performance characteristic which is then subject to specification-oriented testing. However, each element of the model parameter vector represents an independent error source which contributes to performance degradations; thus, the model parameter vector can be viewed as a signature of the error sources. In this work, analyzing the error source signature is used to devise a model-based methodology for hard-fault detection and diagnosis. We investigate conditions under which hard-faults are detectable/diagnosable in spite of masking effects due to manufacturing process variations. In particular, we show that taking the model parameter vector as the fault signature is optimal as it minimizes the masking effects and thus maximizes detectability/diagnosibility.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

Notes

  1. The number six refers here to the six-sigma quality paradigm [30].

References

  1. Abell ML, Braselton JP, Rafter JA (1998) Statistics with mathematica. Academic Press

  2. Arabi K, Kaminska B (1997) Oscillation built-in self test (OBIST) scheme for functional and structural testing of analog and mixed-signal integrated circuits. In: Proc ITC, Int Test Conf, Washington, DC, USA, pp 786–795, November

  3. Bhattacharya S, Senguttuvan R, Chatterjee A (2005) Production test technique for measuring BER of ultra-wideband (UWB) devices. IEEE Trans Microwave Theor Tech 53(11):3474–3481, November

    Article  Google Scholar 

  4. Brosa AM, Figueras J (1999) On maximizing the coverage of catastrophic and parametric faults. In: Proc ETW, European Test Workshop pp 123–128, May

  5. Burns M, Roberts GW (2001) An introduction to mixed-signal IC test and measurement. Oxford series in electrical and computer engineering, 1st edn. Oxford Univ. Press, New York

    Google Scholar 

  6. Charoenrook A, Soma M (1996) A fault diagnosis technique for flash ADC’s. IEEE Trans Circuits Syst II 43(6):445–457, June

    Article  Google Scholar 

  7. Cherubal S, Chatterjee A (2003) Optimal linearity testing of analog-to-digital converters using a linear model. IEEE Trans Circuits Syst part I, 50(3):317–327, March

    Article  Google Scholar 

  8. Crippa P, Turchetti C, Conti M (2002) A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters. IEEE Trans Comput-Aided Des Integr Circuits Syst 21(4):377–394, April

    Article  Google Scholar 

  9. Devarayanadurg G, Soma M, Goteti P, Huynh SD (1999) Test set selection for structural faults in analog IC’s. Trans. CAD of ICs and Systems 18(7):1026–1039, July

    Article  Google Scholar 

  10. Fedi G, Manetti S, Piccirilli MC, Starzyk J (1999) Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits. IEEE Trans Circuits Syst part I 46(7):779–787, July

    Article  Google Scholar 

  11. Felt E, Narayan A, Sangiovanni-Vlncentelli A (1994) Measurement and modeling of MOS transistor current mismatch in analog IC’s. In: Proc ICCAD, Int Conf on Computer-Aided Design, pp 272–277, November

  12. Golub GH, van Loan CF (1996) Matrix computations, 3rd edn. Johns Hopkins Univ. Press, Baltimore

    MATH  Google Scholar 

  13. Jarwala M, Tsai S-J (1991) A framework for design for testability of mixed analog/digital circuits. In: Proc CICC, Custom Integrated Circuits Conf, pp 13.5/1–13.5/4, May

  14. Lechner A, Richardson A, Hermes B (2001) Short circuit faults in state-of-the-art ADCs—are they hard or soft? In: Proc ATS, Asian Test Symp, Kyoto, Japan, pp 417–422, November

  15. Lindermeir WM, Vogels TJ, Graeb HE (1998) Analog test design with IDD measurements for the detection of parametric and catastrophic faults. In: Proc DATE, Conf on Design, Automation and Test in Europe, Paris, France, pp 822–827, February

  16. McSweeney D, McGovern J, Wegener C, Kennedy MP, O’Connell L, O’Riordan JJ (2004) Model-based reduction of DAC test-time. In: Proc ICTW, IEEE IC Test Workshop, pp75–80. Limerick, ISBN 0-9548342-0-8, September

  17. Olbrich T, Mozuelos R, Richardson A, Bracho S (1996) Design-for-test (DfT) study on a current mode DAC. IEEE Proc Circ Devices Syst 143(6):374–379, December

    Article  MATH  Google Scholar 

  18. O’Sullivan K, Gorman C, Hennessy M, Callaghan V (2004) A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm2. IEEE J Solid-State Circuits 39(7):1064–1072, July

    Article  Google Scholar 

  19. Peralias EJ, Rueda A, Huertas JL (2001) Structural testing of pipelined analog to digital converters. In: Proc ISCAS, Int Symp on Circuits and Systems, pp 436–439. Sydney, Australia, May

  20. Renovell M, Azais F, Bodin J-C, Bertrand Y (1999) Functional and structural testing of switched-current circuits. In: Proc ETW, European Test Workshop, pp 22–27, May

  21. Sachdev M, Atzema B (1995) Industrial relevance of analogue IFA: a fact or a fiction. In: Proc ITC’95, Int Test Conf, Washington, DC, USA, pp 61–70, October

  22. Savir J, Zhen G (2003) Test limitations of parametric faults in analog circuits. IEEE Trans Instrum Meas 52(5):1444–1454, October

    Article  Google Scholar 

  23. Slamani M, Kaminska B (1992) Analog circuit fault diagnosis based on sensitivity computation and functional testing. IEEE Des Test Comput 9(1):30–39, March

    Article  Google Scholar 

  24. Stenbakken GN, Souders TM (1985) Modeling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817

  25. Stenbakken GN, Souders TM (1994) Developing linear error models for analog devices. IEEE Trans Instrum Meas IM-43(2):157–163

    Article  Google Scholar 

  26. Straube B, Müller B, Vermeiren W, Hoffmann Ch, Sattler S (2000) Analogue fault simulation by aFSIM. In: User forum, DATE, Conf on Design, Automation and Test in Europe, pp 205–210, March

  27. Straube B, Vermeiren W, Coym T, Lindig M, Grobelny L, Lerch A (2006) Fault diagnosis of analog integrated circuits using an analog fault simulator. In: Proc IMSTW, Int Mixed Signal Testing Workshop, Edingburgh, Scotland, UK, pp 34–38, June 2006

  28. The Institute of Electrical and Electronics Engineers, Inc., New York (2000) IEEE Std 1241-2000, IEEE standard for terminology and test methods for analog-to-digital converters, December

  29. Tseng C-W, Chen R, Nigh P, McCluskey E (2001) MINVDD testing for weak CMOS ICs. In: Proc VTS, VLSI Test Symposium, pp 339–344

  30. Tobias PA (1991) A six sigma program implementation. In: Proc CICC, Custom Integrated Circuits Conference, pages 29.1/1–4, San Diego, CA, USA, pp 12–15, May

  31. Vargha B, Schoukens J, Rolain Y (2003) Modelling of partially-segmented D/A converters. In: Proc IMTC, vol 1 of Instrumentation and Measurement Technology Conf. pp 628–633, May

  32. Wagdy MF (1989) Diagnosing ADC nonlinearity at the bit level. IEEE Trans Instrum Meas 38(6):1139–1141, December

    Article  Google Scholar 

  33. Wegener C (2003) Applications of linear modeling to testing and characterizing D/A and A/D converters. PhD thesis, University College Cork, Dept. Microelectr. Eng., November

  34. Wegener C, Kennedy MP (2003) Linear model-based error identification and calibration for data converters. In: Proc DATE, Conf on Design, Automation and Test in Europe, Munich, Germany, pp 630–635, March

  35. Wegener C, Kennedy MP (2004) Linear model-based testing of ADC nonlinearities. IEEE Trans Circuits Syst I, 51(1):213–217, January

    Article  Google Scholar 

  36. Wegener C, Kennedy MP (2005) Overcoming test setup limitations by applying model-based testing to high-precision ADCs. J Electron Test: Theory and Applications (JETTA) 21(3):299–310, June

    Google Scholar 

  37. Wegener C, Kennedy MP (2006a) Test development through defect and test escape level estimation for data converters. J Electron Test (JETTA) 22:313–324

    Article  Google Scholar 

  38. Wegener C, Kennedy MP (2006b) Detecting hard-faults masked by manufacturing process variations: a DAC example. In: Proc ETS, European Test Symposium, Southampton, UK, pp 6, May

  39. Wegener C, Kennedy MP, Straube B (2001) Process deviations and spot defects: two aspects of test and test development for mixed-signal circuits. J Electron Test 17(5):409–416, October

    Article  Google Scholar 

  40. Williams RH, Hawkins CF (1993) The economics of guardband placement. In: Proc ITC, Int Test Conf, pp 218–224

  41. Wrixon A, Kennedy MP (1999) A rigorous exposition of the LEMMA method for analog and mixed-signal testing. IEEE Trans Instrum Meas IM-48(5):978–985, October

    Article  Google Scholar 

Download references

Acknowledgment

The authors acknowledge the support by Science Foundation Ireland Grant 02IN.1I045s1.

Author information

Authors and Affiliations

  1. Infineon Technologies AG, 81726, Munich, Germany

    Carsten Wegener

  2. Department of Microelectronic Engineering, University College Cork, Cork, Ireland

    Michael Peter Kennedy

Authors
  1. Carsten Wegener
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Michael Peter Kennedy
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Carsten Wegener.

Additional information

Responsible Editor: M. Lubaszewski

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wegener, C., Kennedy, M.P. Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing. J Electron Test 23, 513–525 (2007). https://doi.org/10.1007/s10836-007-5050-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-007-5050-2

Keywords

Search

Navigation