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Controllability of Static CMOS Circuits for Timing Characterization

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Abstract

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

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Acknowledgments

The authors would like to thank Whitney J. Townsend for helping us design the multipliers. This work was supported in part by the IBM Faculty Partnership Award Program, and in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation (MARCO).

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Authors and Affiliations

  1. The University of Texas at Austin, Austin, TX, USA

    Ramyanshu Datta & Jacob A. Abraham

  2. Freescale Semiconductors, Austin, TX, USA

    Ravi Gupta

  3. ARM Corporation, Austin, TX, USA

    Antony Sebastine

  4. SanDisk Corporation, Milpitas, CA, USA

    Manuel d’Abreu

Authors
  1. Ramyanshu Datta
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  2. Ravi Gupta
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  3. Antony Sebastine
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  4. Jacob A. Abraham
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  5. Manuel d’Abreu
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Corresponding author

Correspondence to Ramyanshu Datta.

Additional information

Responsible Editor: K.-T. Cheng

Antony Sebastine and Ravi Gupta contributed to this paper when they are graduate students at the University of Texas at Austin.

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Datta, R., Gupta, R., Sebastine, A. et al. Controllability of Static CMOS Circuits for Timing Characterization. J Electron Test 24, 481–496 (2008). https://doi.org/10.1007/s10836-007-5059-6

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  • DOI: https://doi.org/10.1007/s10836-007-5059-6

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