Skip to main content
SpringerLink
Log in

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Trans Very Large Scale Integr Syst 13(3):384–395, Mar

    Article  Google Scholar 

  2. Borkar S, et al (2003) Parameter variations and impact on circuits and microarchitecture. Design Automation Conference, pp 338–342

  3. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Boston

    Google Scholar 

  4. Calhoun BH, Honore FA, Chandrakasan A (2003) Design methodology for fine-grained leakage control in MTCMOS. In: International symposium on low power electronics design, Seoul, pp 104–107, 25–27 August

  5. Cheng K-T, Devadas S, Keutzer K (1991) A partial en- hanced scan approach to robust delay-fault test generation for sequential circuits. In: International test conference, Nashville, pp 403–410, 26–30 October

  6. DasGupta S, Eichelberger EB, Williams TW (1978) LSI chip design for testability, digest of technical papers. In: IEEE international solid-state circuits conference, IEEE, Piscataway, pp 216–217, Feb

  7. DasGupta S, Walther RG, Williams TW, Eichelberger EB (1981) An enhancement to LSSD and some applications of LSSD in reliability, availability, and serviceability. In: International symposium on fault-tolerant computing, Portland, pp 32–34, June

  8. Dervisoglu BI, Stong GE (1991) Design for testability: using scanpath techniques for path-delay test and measurement. In: International test conference, Nashville, pp 365–374, 26–30 October

  9. EETimes (2002) EEDesign Article. Delay-fault testing mandatory, author claims. http://www.eedesign.com/story/OEG20021204S0029, Dec

  10. EETimes (2002) EETimes Article. Researchers: time to overhaul design. http://www.eetimes.com/showArticle.jhtml?articleID=18307867, Dec

  11. EETimes (2003) EETimes Article. Scan-based transition-fault test can do job. http://www.eetimes.com/story/OEG20031024S0028, Oct

  12. Gerstendrfer S, Wunderlich H-J (1999) Minimized power consumption for scan-based BIST. In: International test conference, Atlantic City, pp 77–84, 27–30 September

  13. Jahangiri J, Abercrombie D (2005) Meeting nanometer DPM requirements through DFT. In: International symposium on quality of electronic design, San Jose, pp 276–282, 21–23 March

  14. Kuppuswamy R et al (2004) Full hold-scan systems in microprocessors: cost/benefit analysis. Intel Technol J 8(1), Feb

  15. Mao W, Ciletti MD (1994) Reducing correlation to improve coverage of delay faults in scan-path design. IEEE Trans Comput-aided Des Integr Circuits Syst 13(5):638–646, May

    Article  Google Scholar 

  16. Ohtake S, Miwa S, Fujiwara H (2002) A method of test generation for path delay faults in balanced sequential circuits. In: VLSI test symposium, Monterey, pp 321–327, 28 April–2 May

  17. Rearick J (2001) Too much delay fault coverage is a bad thing. In: International test conference, Baltimore, pp 624–633, 30 October–1 November

  18. Roy K, Mukhopadhyay S, Mahmoodi-Meimand H (2003) Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc IEEE 91:305–327, Feb

    Article  Google Scholar 

  19. Savir J (1997) Scan latch design for delay test. In: International test conference, Washington, DC, pp 446–452, 3–5 November

  20. TekuMalla RC, Menon PR (1997) Delay testing with clock control: an alternative to enhanced scan. In: International test conference, Washington, DC, pp 454–462, 3–5 November

  21. University of California (2001) Predictive technology model. http://www-device.eecs.berkeley.edu/~ptm

  22. Wang S, Liu X, Chakradhar ST (2004) Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets. In: Design automation and test in Europe, Paris, pp 1296–1301, 16–20 February

  23. Warnock JD, Huott WV (2005) High-speed level sensitive scan design test scheme with pipelined test clocks. United States Patent 7178075 B2

  24. Zhang A (2006) Modeling custom scan flops in level sensitive scan design. United States Patent 7039843

Download references

Acknowledgment

This research was funded in part by Gigascale Silicon Research Center (GSRC MARCO) and by National Science Foundation (NSF).

Author information

Authors and Affiliations

  1. Electrical Engineering and Computer Science, Case Western Reserve University, 10900 Euclid Avenue, Glennan Building, 514A, Cleveland, OH, 44120, USA

    Swarup Bhunia

  2. Electrical and Computer Engineering, San Francisco State University, San Francisco, CA, USA

    Hamid Mahmoodi

  3. Circuit Reasearch Lab, Intel Corporation, Portland, OR, USA

    Arijit Raychowdhury

  4. Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA

    Kaushik Roy

Authors
  1. Swarup Bhunia
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Hamid Mahmoodi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Arijit Raychowdhury
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Kaushik Roy
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Swarup Bhunia.

Additional information

Responsible Editor: A. D. Singh

Rights and permissions

Reprints and permissions

About this article

Cite this article

Bhunia, S., Mahmoodi, H., Raychowdhury, A. et al. Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J Electron Test 24, 577–590 (2008). https://doi.org/10.1007/s10836-008-5072-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-008-5072-4

Keywords

Search

Navigation