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Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

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Abstract

This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.

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Acknowledgements

The authors gratefully thank the anonymous reviewers whose comments have improved the quality of this paper. This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsis, Inc. and Cadence Design Systems, Inc. The authors’ researches were partially supported by a grant from CASIO Science Promotion Foundation and Grant-in-Aid for Scientific Research (C) No.19560335.

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Authors and Affiliations

  1. Graduate School of Advanced Integration Science, Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba, 263-8522, Japan

    Kazuteru Namba & Hideo Ito

  2. Graduate School of Science and Technology, Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba, 263-8522, Japan

    Yoshikazu Matsui

Authors
  1. Kazuteru Namba
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  2. Yoshikazu Matsui
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  3. Hideo Ito
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Correspondence to Kazuteru Namba.

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Responsible Editors: C. Bolchini and Y.-B. Kim

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Namba, K., Matsui, Y. & Ito, H. Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J Electron Test 25, 97–105 (2009). https://doi.org/10.1007/s10836-008-5080-4

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  • DOI: https://doi.org/10.1007/s10836-008-5080-4

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