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On Built-In Self-Test for Adders

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Abstract

We evaluate some of the previously proposed test approaches for various types of adders in an attempt to find an architecture-independent algorithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self-Test (BIST) approach provides the highest fault coverage for most types of adders and, equally important, it is simple to implement.

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Acknowledgment

This work was sponsored by the National Security Agency under contract H98230-04-C-1177 and supported in part by the National Science Foundation Grant CNS-0708962.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, USA

    Mary D. Pulukuri & Charles E. Stroud

Authors
  1. Mary D. Pulukuri
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  2. Charles E. Stroud
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Correspondence to Mary D. Pulukuri.

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Responsible Editor: K. Saluja

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Pulukuri, M.D., Stroud, C.E. On Built-In Self-Test for Adders. J Electron Test 25, 343–346 (2009). https://doi.org/10.1007/s10836-009-5114-6

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  • DOI: https://doi.org/10.1007/s10836-009-5114-6

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