Qualifying Serial Interface Jitter Rapidly and Cost-effectively

Abstract

High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen in a communication interface, Bit Error Rate (BER) performance is of paramount importance. The bit errors in HSSIs are in large part due to jitter. This paper investigates the topic of accelerating the jitter and BER testing. We first present an under-sampling based transmitter test scheme. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100 ms while the test usually takes seconds. Then we propose a jitter tolerance extrapolation algorithm that enables us to perform the receiver jitter tolerance characterization and production test more than 1,000 times faster. The transmitter and receiver testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with data rates up to 6 Gigabits per second (Gbps). The paper also presents a low cost external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay line. With the novel jitter injection scheme and an FPGA-based Bit Error Rate Tester (BERT), we can validate and test HSSIs with higher data rates, but without the need of high-speed ATE instruments. Using high-speed relays, we can also utilize ATE to provide a more versatile scheme for HSSI validation, characterization and testing.