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MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics

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Abstract

As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to detect small delay defects and to verify the correct temporal behavior of a circuit. In this article, MONSOON, an efficient SAT-based approach for generating non-robust and robust test patterns for path delay faults is presented. MONSOON handles tri-state elements and environmental constraints occurring in industrial practice using multiple-valued logics. Structural techniques increase the efficiency of the algorithm. A comparison with a state-of-the-art approach shows a significant speed-up. Experimental results for large industrial circuits demonstrates the feasibility and robustness of MONSOON.

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Notes

  1. In the following, the term SAT solver always means a CNF-based SAT solver.

  2. Parts of this article, i.e. the SAT formulation for multiple-valued logics, have been published in [12].

  3. For a detailed discussion about the classification of PDF tests, the reader is referred to [20].

  4. According to their description, this simplification is done in [24].

  5. This procedure can be directly extended to the functional sensitization criterion. However, this article is restricted to the non-robust and robust sensitization criterion.

  6. To the best of our knowledge, no free PDF test generator that can generate robust tests and/or can handle static values and industrial constraints is available for comparison.

  7. A restart is defined as a certain number of conflicts (100 at the beginning). After each restart, the number of conflicts is increased (by 50%).

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Acknowledgment

This work was supported in part by the German Federal Ministry of Education and Research (BMBF) in the Project MAYA under the contract number 01M3172B and by the German Research Foundation (DFG) under contract number DR 287/15-1.

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Authors and Affiliations

  1. University of Bremen, 28359, Bremen, Germany

    Stephan Eggersglüß, Görschwin Fey & Rolf Drechsler

  2. Mentor Graphics Development GmbH, 21079, Hamburg, Germany

    Andreas Glowatz, Friedrich Hapke & Juergen Schloeffel

Authors
  1. Stephan Eggersglüß
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  2. Görschwin Fey
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  3. Andreas Glowatz
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  4. Friedrich Hapke
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  5. Juergen Schloeffel
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  6. Rolf Drechsler
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Correspondence to Stephan Eggersglüß.

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Responsible Editor: M. Hsiao

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Eggersglüß, S., Fey, G., Glowatz, A. et al. MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J Electron Test 26, 307–322 (2010). https://doi.org/10.1007/s10836-010-5146-y

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  • DOI: https://doi.org/10.1007/s10836-010-5146-y

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