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Chiba Scan Delay Fault Testing with Short Test Application Time

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Abstract

Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT.

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Notes

  1. Path delay faults that are not sensitizable with LoC [6] need not be tested.

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Acknowledgments

The authors gratefully thank a graduate of our laboratory HaiYing Jin for her valuable comments and suggestions on earlier versions of this paper. This research was partially supported by a grant from CASIO Science Promotion Foundation and the Grant-in-Aid for Young Scientists (B) No. 21700053.

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Authors and Affiliations

  1. Chiba University, 1-33 Yayoi-cho, Inage-ku, Chiba, 263-8522, Japan

    Kazuteru Namba & Hideo Ito

Authors
  1. Kazuteru Namba
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  2. Hideo Ito
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Correspondence to Kazuteru Namba.

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Responsible Editor: M. Goessel

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Namba, K., Ito, H. Chiba Scan Delay Fault Testing with Short Test Application Time. J Electron Test 26, 667–677 (2010). https://doi.org/10.1007/s10836-010-5177-4

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  • DOI: https://doi.org/10.1007/s10836-010-5177-4

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