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Masking of X-Values by Use of a Hierarchically Configurable Register

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Abstract

In this paper we consider masking of unknowns (X-values) for VLSI circuits. We present a new hierarchical method of X-masking which is a major improvement of the method proposed in [4], called WIDE1. By the method proposed, the number of observable scan cells is optimized and data volume for X-masking can be significantly reduced in comparison to WIDE1. This is demonstrated for three industrial designs. In cases where all X-values have to be masked the novel approach is especially efficient.

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Notes

  1. Instead of an AND-gate all logic functions with controlling values can be used [1].

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Acknowledgment

This work has been funded within the MAYA project under label 01M3063A by the German Federal Ministry for Education and Research (BMBF). The authors are grateful to the reviewers for the helpful comments.

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Authors and Affiliations

  1. University of Potsdam, August-Bebel-Strasse 89, 14482, Potsdam, Germany

    Thomas Rabenalt & Michael Goessel

  2. Infineon Technologies AG, Am Campeon 1-12, 85579, Neubiberg, Germany

    Andreas Leininger

Authors
  1. Thomas Rabenalt
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  2. Michael Goessel
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  3. Andreas Leininger
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Correspondence to Thomas Rabenalt.

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Responsible Editor: C. Metra

A provisional version of this paper was presented at the European Test Symposium 2009

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Rabenalt, T., Goessel, M. & Leininger, A. Masking of X-Values by Use of a Hierarchically Configurable Register. J Electron Test 27, 31–41 (2011). https://doi.org/10.1007/s10836-010-5179-2

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  • DOI: https://doi.org/10.1007/s10836-010-5179-2

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