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Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths

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Abstract

This article presents experimental results for a clock-timing methodology that allows timing characterization and testing of high-speed pipelined datapaths using slow-speed testers. The technique uses a clock-timing circuit to control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9 ps in 0.18 μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit used to generate and control test mode clocks.

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Authors and Affiliations

  1. TSMC Design Technology Canada, Ottawa, Canada

    Muhammad Nummer

  2. Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Canada

    Manoj Sachdev

Authors
  1. Muhammad Nummer
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  2. Manoj Sachdev
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Correspondence to Muhammad Nummer.

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Responsible Editor: S. T. Chakradhar

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Nummer, M., Sachdev, M. Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. J Electron Test 27, 9–17 (2011). https://doi.org/10.1007/s10836-010-5186-3

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  • DOI: https://doi.org/10.1007/s10836-010-5186-3

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