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Analysis of Resistive Open Defects in Drowsy SRAM Cells

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Abstract

New fault behaviors can emerge with the introduction of a drowsy mode to SRAMs. In this work, we show that, in addition to the data-retention faults that can occur during the drowsy mode, open defects in SRAM cells can also result in new fault behaviors when a memory is accessed immediately after wake-up. We first describe these new read-after-drowsy (RAD) fault behaviors and derive their corresponding fault primitives (FPs). Then, we propose a new March test, called March RAD, by inserting drowsy operations to a traditional test algorithm. Finally, the impact of the standby supply voltage on triggering the drowsy faults in SRAM cells is investigated. It is shown that, as the supply voltage is reduced in the drowsy mode to further cut down leakage, open defects with a parasitic resistance as small as 100 K Ω begin to cause faults.

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References

  1. Qin H, Cao Y, Markovic D, Vladimirescu A, Rabaey J (2004) SRAM leakage suppression by minimizing standby supply voltage. In: Proceedings on 5th international symposium on quality electronic design, pp 55–60

  2. Kim NS, Flautner, K, Blaauw D, Mudge T (2004) Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans Very Large Scale Integr(Vlsi) Syst 12(2):167–184

    Article  Google Scholar 

  3. Agarwal A, Li H, Roy K (2003) A single-Vt low-leakage gated-ground cache for deep submicron. IEEE J Solid-State Circuits 38(2):319–328

    Article  Google Scholar 

  4. Konstadinidis G, Tremblay M, Chaudhry S, Rashid M, Lai P, Otaguro Y, Orginos Y, Parampalli S, Steigerwald M, Gundala S, Pyapali R, Rarick L, Elkin I, Ge Y, Parulkar I (2009) Architecture and physical implementation of a third generation 65 nm, 16 core, 32 thread chip-multithreading sparc processor. IEEE J Solid-State Circuits 44(1):7–17

    Article  Google Scholar 

  5. Pavlov A, Sachdev M, De Gyvez J (2006) Weak cell detection in deep-submicron SRAMs: A programmable detection technique. IEEE J Solid-State Circuits 41(10): 2334–2343

    Article  Google Scholar 

  6. Mak T, Bhattacharya D, Prunty C, Roeder B, Ramadan N, Ferguson J, Yu J (1998) Cache RAM inductive fault analysis with fab defect modeling. In: Proceedings international test conference, pp 862–871

  7. Needham W, Prunty C, Yeoh EH (1998) High volume microprocessor test escapes, an analysis of defects our tests are missing. In: Proceedings international test conference, pp 25–34

  8. Yang J, Wang B, Wu Y, Ivanov A (2006) Fast detection of data retention faults and other SRAM cell open defects. IEEE Trans Comput-Aided Des Integr Circuits Syst 25(1):167–180

    Article  Google Scholar 

  9. Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Hage-Hassan M (2004) Resistive-open defects in embedded-sram core cells: analysis and march test solution. In: ATS ’04: proceedings of the 13th Asian test symposium. IEEE Computer Society, Washington, pp 266–271

  10. Kundu S, Sengupta S, Galivanche R (2000) Test challenges in nanometer technologies. In: Proceedings IEEE European test workshop, pp 83–90

  11. Pei W, Jone W-B, Hu Y (2007) Fault modeling and detection for drowsy SRAM caches. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(6):1084–1100

    Article  Google Scholar 

  12. van de Goor A, Al-Ars Z (2000) Functional memory faults: a formal notation and a taxonomy. In: Proceedings 18th IEEE VLSI test symposium, pp 281–289

  13. Al-Ars Z, van de Goor A (2001) Static and dynamic behavior of memory cell array opens and shorts in embedded drams. In: DATE ’01: proceedings of the conference on design, automation and test in Europe. IEEE, Piscataway, pp 496–503

    Chapter  Google Scholar 

  14. Borri S, Hage-Hassan M, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2005) Analysis of dynamic faults in embedded-srams: Implications for memory test. J Electro Testing (JETTA) 21(2):169–179

    Article  Google Scholar 

  15. Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Virazel A (2009) Advanced test methods for SRAMs- effective solutions for dynamic fault detection in nanoscaled technologies. Springer

  16. Hamdioui S, Van De Goor A (2000) An experimental analysis of spot defects in SRAMs: realistic fault models and tests. In: Proceedings of the Ninth asian test symposium, (ATS 2000), pp 131–138

  17. Ding L, Mazumder P (2003) The impact of bit-line coupling and ground bounce on cmos sram performance. In: Proceeding. 16th international conference on VLSI design, pp 234–239

  18. Chang J, Huang M, Shoemaker J, Benoit J, Chen S-L, Chen W, Chiu S, Ganesan R, Leong G, Lukka V, Rusu S, Srivastava D (2007) The 65-nm 16-MB shared on-die L3 cache for the dual-core Intel Xeon processor 7100 series. IEEE J Solid-State Circuits 42(4):846–852

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Concordia University, Montreal, QC, H3G 1M8, Canada

    Afshin Nourivand & Asim J. Al-Khalili

  2. Department of Electrical Engineering, Ecole Polytechnique de Montreal, Montreal, QC, H3C 3A7, Canada

    Yvon Savaria

Authors
  1. Afshin Nourivand
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  2. Asim J. Al-Khalili
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  3. Yvon Savaria
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Correspondence to Afshin Nourivand.

Additional information

Responsible Editor: M. Sachdev

This work was supported by the Natural Sciences and Engineering Research Council of Canada (NSERC), the Microsystems Strategic Alliance of Quebec (ReSMiQ), and the Canada Research Chairs (CRC) Program via grants and scholarships.

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Nourivand, A., Al-Khalili, A.J. & Savaria, Y. Analysis of Resistive Open Defects in Drowsy SRAM Cells. J Electron Test 27, 203–213 (2011). https://doi.org/10.1007/s10836-011-5206-y

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  • DOI: https://doi.org/10.1007/s10836-011-5206-y

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