Skip to main content
SpringerLink
Log in

Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Extended finite state machines (EFSMs) can be efficiently adopted to model the functionality of complex designs without incurring the state explosion problem typical of the more traditional FSMs. However, traversing an EFSM can be more difficult than an FSM because the guards of EFSM transitions involve both primary inputs and registers. This paper first analyzes the hardness of traversing an EFSM according to the characteristics of its transitions. Then, it presents a methodology to generate an EFSM which is easy to be traversed. Finally, it proposes a functional deterministic automatic test pattern generation (ATPG) approach that exploits such EFSMs for functional verification. In particular, the ATPG approach joins backjumping, learning, and constraint solving to (i) early identify possible symptoms of design errors by efficiently exploring the whole state space of the design under verification (DUV), and (ii) generate effective input sequences to be used in further verification steps which require to stimulate the DUV. The effectiveness of the proposed approach is confirmed in the experimental result section, where it is compared with both genetic and pseudo-deterministic techniques.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Listing 1
Fig. 11
Listing 2
Fig. 12

Similar content being viewed by others

Notes

  1. This may happen if iv is the last vector of s.

  2. If the unsatisfiability of t depends on more than one register, the backjumping procedure is repeated for each of them.

References

  1. Cheng K, Krishnakumar A (1996) Automatic generation of functional vectors using the extended finite state machine model. ACM Transact Des Automat Electron Syst 1(1):57–79

    Article  Google Scholar 

  2. Chipounov V, Georgescu V, Zamfir C, Candea G (2009) Selective symbolic execution. In: Proc. of workshop on hot topics dependable systems

  3. Corno F, Cumani G, Sonza Reorda M, Squillero G (2001) Effective Techniques for High-Level ATPG. In: Proc of IEEE ATS, pp 225–230

  4. Cytron R, Ferrante J, Rosen B, Wegman M, Zadeck F (1991) Efficiently computing static single assignment form and the control dependence graph. ACM Trans Program Lang Syst (TOPLAS) 13(4):451–490

    Article  Google Scholar 

  5. Di Guglielmo G, Fummi F, Marconcini C, Pravadelli G (2006) Improving Gate-Level ATPG by Traversing Concurrent EFSMs. In: Proc of IEEE VTS

  6. Dijkstra E (1959) A note on two problems in connexion with graphs. Numer Math 1:269–271

    Article  MathSciNet  MATH  Google Scholar 

  7. Duale A, Uyar U (2004) A method enabling feasible conformance test sequence generation for EFSM models. IEEE Trans Comput 53(5):614–627

    Article  Google Scholar 

  8. Ferrandi F, Fummi F, Sciuto D (1998) Implicit test generation for behavioral vhdl models. In: Proc of IEEE ITC, pp 436–441

  9. Fin A, Fummi F (2003) Genetic algorithms: the philosopher’s stone or an effective solution for high-level TPG? In: Proc of IEEE HLDVT, pp 163–168

  10. Fummi F, Marconcini C, Pravadelli G (2004) Functional verification based on the EFSM model. In: Proc of IEEE HLDVT, pp 69–74

  11. Gajski D, Zhu J, Domer R (1997) Essential issue in codesign. Thecnical report ICS-97-26, University of California, Irvine

  12. Gajski D, Dutt N, Allen S, Wu C, Lin Y (1992) High-level synthesis: introduction to chip and system design, 1st edn. Kluwer Academic Publishers

  13. Gaschnig J (1979) Performance measurement and analysis of certain search algorithms. PhD thesis, Department of Computer Science, CarnegieMellon University, Pittsburgh

  14. Ghosh I, Fujita M (2001) Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(3):402–415

    Article  Google Scholar 

  15. Giomi J (1995) Finite state machine extraction from hardware description languages. In: ASIC conference and exhibit, 1995. Proceedings of the eighth annual IEEE international, pp 353–357

  16. Hansen T, Schachte P, Søndergaard H (2009) State Joining and Splitting for the Symbolic Execution of Binaries. In: Runtime Verification. Springer, pp 76–92

  17. Hierons R, Kim T-H, Ural H (2002) Expanding an extended finite state machine to aid testability. In: Proc of IEEE COMPSAC, pp 334–339

  18. IEEE Computer Society (2008) IEEE standard for the functional language e. IEEE Computer Society

  19. Iyer M, Parthasarathy G, Cheng K-T (2005) Efficient conflict-based learning in an RTL circuit constraint solver. In: Proc of IEEE DATE, pp 666–671

  20. Jaffar J, Maher M (1994) Constraint logic programming: a survey. J Log Program 19:503–581

    Article  MathSciNet  Google Scholar 

  21. King J (1976) Symbolic execution and program testing. Commun ACM 19(7):385–394

    Article  MATH  Google Scholar 

  22. Kroening D, Strichman O (2008) Decision procedures: an algorithmic point of view. Springer, New York

    MATH  Google Scholar 

  23. Lee D, Yannakakis M (1992) Online minimization of transition systems. In: Proc of ACM symposium on the theory of computing, pp 264–274

  24. Lin X, Pomeranz I, Reddy S (1999) Techniques for improving the efficiency of sequential circuit test generation. In: Proc of IEEE/ACM ICCAD, pp 147–151

  25. Lingappan L, Ravi S, Jha N (2003) Test generation for non-separable RTL controller-datapath circuits using a satisfiability based approach. In: Proc of IEEE ICCD, pp 187–193

  26. Mentor Graphics inFact. http://www.mentor.com/products/fv/infact/

  27. Mentor Graphics Questa MVC. http://www.mentor.com/products/fv/questa-mvc/

  28. Moskewicz M, Madigan C, Zhao Y, Zhang L, Malik S (2001) Chaff: engineering an efficient sat solver. In: Proc of ACM/IEEE DAC, 530–535

  29. Myers G (1979) The art of software testing. Wiley-Interscience, New York

    Google Scholar 

  30. Navabi Z (1993) VHDL: analysis and modeling of digital systems. McGraw-Hill

  31. Padmanabhuni S (1999) Extended analysis of intelligent backtracking algorithms for the maximal constraint satisfaction problem. In: Proc of IEEE CCECE, pp 1710–1715

  32. Pearl J, Korf R (1987) Search techniques. Annu Rev Comput Sci 2(1):451–467

    Article  Google Scholar 

  33. Politecnico di Torino (1999) ITC-99 Benchmarks. In: http://www.cad.polito.it/tools/itc99.html

  34. Regimbal S, Lemire J-F, Savaria Y, Bois G, Aboulhamid E, Baron A (2003) Automating functional coverage analysis based on an executable specification. In: Proc of IEEE international workshop on system-on-chip for real-time applications, pp 228–234

  35. Roy S, Ramesh S, Chakraborty S, Nakata T, Rajan S (2002) Functional verification of system on chips-practices, issues and challenges. In: Proc of IEEE ASP-DAC, pp 11–13

  36. Russel S, Norvig P (2002) Artificial intelligence: a modern approach. Prentice Hall

  37. Sallay B, Petri A, Tilly K, Pataricza A, Sziray J (1996) High level test pattern generation for vhdl circuits. In: Proc of IEEE ETW, pp 201–205

  38. Tao Y (2009) An introduction to assertion-based verification. In: Proc of IEEE international conference on ASIC, pp 1318–1323

  39. Uyar U, Duale A (1997) Modeling VHDL specifications as consistent EFSMs. In: Proc of IEEE MILCOM, pp 740–744

  40. Uyar U, Duale A (1999) Resolving inconsistencies in EFSM-modeled specifications. In: Proc of IEEE MILCOM, pp 135–139

  41. Uyar U, Duale A (2000) Test generation form EFSM models of complex army protocols with inconsistencies. In: Proc of IEEE MILCOM, pp 340–346

  42. Wallace M, Veron A (1994) Two problems-two solutions: one system-ECLiPSe. In: IEE Colloquium on advanced software technologies for scheduling, pp 1–3

  43. Wu Q, Hsiao M (2004) Efficient ATPG for design validation based on partitioned state exploration histories. In: Proc of IEEE VTS, pp 389–394

  44. Xin F, Ciesielski M, Harris I (2005) Design validation of behavioral vhdl descriptions for arbitrary fault models. In: Proc of IEEE ETS, pp 156–161

  45. Zhang L, Ghosh I, Hsiao M (2003) Efficient Sequential ATPG for Functional RTL Circuits. In: Proc of IEEE ITC, pp 290–298

Download references

Author information

Authors and Affiliations

  1. Dipartimento di Informatica, Università di Verona, Strada Le Grazie 15, 37134, Verona, Italy

    Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi & Graziano Pravadelli

Authors
  1. Giuseppe Di Guglielmo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Luigi Di Guglielmo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Franco Fummi
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Graziano Pravadelli
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Giuseppe Di Guglielmo.

Additional information

Responsible Editor: J. P. Hayes

This work has been partially supported by European project COCONUT FP7-2007-IST-1-217069.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Guglielmo, G.D., Guglielmo, L.D., Fummi, F. et al. Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs. J Electron Test 27, 137–162 (2011). https://doi.org/10.1007/s10836-011-5209-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5209-8

Keywords

Search

Navigation