Abstract
This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.
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Abbreviations
- ADC:
-
Analog to digital converter
- ATE:
-
Automated test equipment
- BI:
-
Burn-in
- BICS:
-
Built-in current sensor
- BIST:
-
Built-in self test
- CUT:
-
Circuit under test
- DBT:
-
Defect based testing
- DfT:
-
Design for test
- GOS:
-
Gate oxide short
- IDD:
-
Current test
- IDDQ:
-
Quiescent current test
- IDDT:
-
Transient current test
- IDDX:
-
Dynamic current test
- OA:
-
Operational amplifier
- PDF:
-
Probability density function
- SI:
-
Switched current
- SiP:
-
System in package
- SoC:
-
System on chip
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Acknowledgments
This work was funded by the Spanish Comisión Interministerial de Ciencia y Tecnología under the projects TIC-2001-0619 and TEC2007-65588.
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Mozuelos, R., Lechuga, Y., Martínez, M. et al. Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor. J Electron Test 27, 177–192 (2011). https://doi.org/10.1007/s10836-011-5214-y
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DOI: https://doi.org/10.1007/s10836-011-5214-y