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Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs

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Abstract

An efficient two-phase calibration technique for 1-bit/stage pipelined Analog–to–Digital Converters (ADCs) is presented in this paper. The proposed technique employs linear histogram testing to collect the required information to calibrate the non-ideal ADC output behavior induced by capacitor mismatch and comparator offset. In the first phase, it calibrates the missing-decision-level errors by amplification gain reduction. Unlike previous works, which require large capacitor arrays, only few switches are added to the circuit. The second phase eliminates missing-transition levels (missing codes). It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both static and dynamic performances.

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Authors and Affiliations

  1. Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, 31040, Taiwan

    Xuan-Lun Huang

  2. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 10617, Taiwan

    Ping-Ying Kang, Yuan-Chi Yu & Jiun-Lang Huang

Authors
  1. Xuan-Lun Huang
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  2. Ping-Ying Kang
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  3. Yuan-Chi Yu
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  4. Jiun-Lang Huang
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Corresponding author

Correspondence to Xuan-Lun Huang.

Additional information

Responsible Editor: A. Ivanov

Preliminary results of the proposed technique were published in [10] and [11]. In this paper, more detailed analysis and more thorough simulations are performed.

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Huang, XL., Kang, PY., Yu, YC. et al. Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs. J Electron Test 27, 441–453 (2011). https://doi.org/10.1007/s10836-011-5231-x

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  • DOI: https://doi.org/10.1007/s10836-011-5231-x

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