Skip to main content
SpringerLink
Log in

Optimization Methods for Post-Bond Testing of 3D Stacked ICs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Banerjee K et al (2001) 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc IEEE 89(5):602–633

    Article  Google Scholar 

  2. Black B, Nelson DW, Webb C, Samra N (2004) 3D processing technology and its impact on iA32 microprocessors. In: Proceedings international conference on computer design (ICCD), pp 316–318

  3. Chen Y, Niu D, Xie Y, Chakrabarty K (2010) Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. In: Proc. IEEE/ACM international conference on CAD, pp 471–476

  4. Chen Y, Niu D, Xie Y, Chakrabarty K (2010) Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. In: Computer-aided design, pp 471–476

  5. Coffman EG Jr, Garey MR, Johnson DS, Tarjan RE (1980) Performance bounds for level-oriented two-dimensional packing algorithms. SIAM J Comput 9:809–826

    MathSciNet  Google Scholar 

  6. Davis WR et al (2005) Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des Test Comput 22(6):498–510

    Article  Google Scholar 

  7. Dong X, Xie Y (2009) System-level cost analysis and design exploration for 3D ICs. In: Proceedings of Asia-South Pacific design automation conference (ASP-DAC), pp 234–241

  8. Dong X, Xie Y (2010) System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs). In: Proc. Asia and South Pacific design automation conf. (ASP-DAC), pp 234–241

  9. FICO. Xpress-MP. http://www.fico.com/en/Products/DMTools/Pages/FICO-Xpress-Optimization-Suite.aspx

  10. Garey MR, Johnson DS (1979) Computers and intractability a guide to the theory of NP-completeness. Freeman, New York

    MATH  Google Scholar 

  11. Goel SK, Marinissen EJ (2003) Control-aware test architecture design for modular SOC testing. In: European test workshop, pp 57–62

  12. Goel SK, Marinissen EJ (2003) SOC test architecture design for efficient utilization of test bandwidth. ACM Trans Des Autom Electron Syst 8(4):399–429

    Article  Google Scholar 

  13. Goel SK, Marinissen EJ, Sehgal A, Chakrabarty K (2009) Testing of SOCs with hierarchical cores: common fallacies, test-access optimization, and test scheduling. IEEE Trans Comput 58:409–423

    Article  MathSciNet  Google Scholar 

  14. Jiang L, Huang L, Xu Q (2009) Test architecture design and optimization for three-dimensional SoCs. In: Design, automation, and test in Europe, pp 220–225

  15. Jiang L, Xu Q, Chakrabarty K, Mak TM (2009) Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. In: Proc. IEEE international conference on computer-aided design, pp 191–196

  16. Jiang L, Liu Y, Duan L, Xie Y, Xu Q (2010) Modeling TSV open defects in 3D-stacked DRAM. In: Proc. IEEE international test conference (ITC), paper 6.1

  17. Jiang L, Ye R, Xu Q (2010) Yield enhancement for 3D-stacked memory by redundancy sharing across dies. In: Computer-aided design, pp 230–234

  18. Kang U et al (2009) 8Gb 3D DDR3 DRAM using through-silicon-via technology. In: Proceedings international solid state circuits conference (ISSCC), pp 130–132

  19. Lee H-HS, Chakrabarty K (2009) Test challenges for 3D integrated circuits. IEEE Des Test Comput 26:26–35

    Article  Google Scholar 

  20. Liu CC, Ganusov I, Burtscher M, Tiwari S (2005) Bridging the processor-memory performance gap with 3D IC technology. IEEE Des Test Comput 22(6):556–564

    Article  Google Scholar 

  21. Lo C-Y, Hsing Y-T, Deng L-M, Wu C-W (2010) SOC test architecture and method for 3-D ICs. In: Computer-aided design of integrated circuits and systems, pp 1645–1649

  22. Loh G, Xie Y, Black B (2007) Processor design in 3D die stacking technologies. Ieee Micro 27(3):31–48

    Article  Google Scholar 

  23. Marinissen EJ, Zorian Y (2009) Testing 3D chips containing through-silicon vias. In: International test conference, E 1.1

  24. Marinissen EJ, Iyengar V, Chakrabarty K (2002) A set of benchmarks for modular testing of SOCs. In: International test conference, pp 519–528

  25. Marinissen EJ, Verbree J, Konijnenburg M (2010) A structured and scalable test access architecture for TSV-based 3D stacked ICs. In: VLSI test symposium

  26. Noia B, Chakrabarty K, Xie Y (2009) Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs. In: Proc. IEEE international conference on computer design, pp 70–77

  27. Noia B, Goel SK, Chakrabarty K, Marinissen EJ, Verbree J (2010) Test-architecture optimization for TSV-based 3D stacked ICs. In: European test symposium

  28. Weerasekera R et al (2007) Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. In: Int. conference on computer-aided design, pp 212–219

  29. Taouill M, Hamdioui S, Beenakker K, Marinissen EJ (2010) Test cost analysis for 3D die-to-wafer stacking. In: Proc. Asian test symposium, pp 435–441

  30. Wu X, Chen Y, Chakrabarty K, Xie Y (2008) Test-access mechanism optimization for core-based three-dimensional SOCs. In: IEEE international conference on computer design, pp 212–218

  31. Xie Y, Loh GH, Bernstein K (2006) Design space exploration for 3D architectures. J Emerg Technol Comput Syst 2(2):65–103

    Article  Google Scholar 

Download references

Acknowledgments

This research was supported in part by a Ph.D. Fellowship and contract number 2011-TJ-2118 from the Semiconductor Research Corporation (SRC), and by the National Science Foundation under grant number CCF-1017391.

Author information

Authors and Affiliations

  1. Duke University, Durham, NC, 27708, USA

    Brandon Noia & Krishnendu Chakrabarty

  2. Kapeldreef 75, 3001, Leuven, Belgium

    Erik Jan Marinissen

Authors
  1. Brandon Noia
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Krishnendu Chakrabarty
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Erik Jan Marinissen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Brandon Noia.

Additional information

Responsible Editor: Y. Zorian

Appendix

Appendix

For the sake of completeness, we present the complete ILP models for \(P^{H}_{\rm MTS}\), \(P^S_{\rm MTS}\), and \(P^H_{\rm DTSV,||}\).

Fig. 13
figure 13

ILP model for the 3D TAM optimization Problem \(P^H_{\rm MTS}\)

Full size image
Fig. 14
figure 14

ILP model for 3D TAM optimization Problem \(P^S_{\rm MTS}\)

Full size image
Fig. 15
figure 15

ILP model for 3D TAM optimization problem \(P^H_{\rm DTSV,||}\)

Full size image

Rights and permissions

Reprints and permissions

About this article

Cite this article

Noia, B., Chakrabarty, K. & Marinissen, E.J. Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J Electron Test 28, 103–120 (2012). https://doi.org/10.1007/s10836-011-5233-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5233-8

Keywords

Search

Navigation