Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits

Abstract

Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elasto-plastic behavior on the induction of stress in 3D crystalline silicon (Si) systems incorporating Cu through-silicon vias (TSVs). Using a linear isotropic hardening model, simulations of thermal annealing cycles in Cu TSVs indicate that, for sufficient anneal temperatures, plastic yield within the Cu leads to substantial residual stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed with experimental Raman microscopy measurements of post-anneal stress profiles in Si near isolated 5 × 25 μm cylindrical TSVs on a 300 mm Si wafer. Simulations were expanded to investigate the impact of Cu plasticity (yield stress and tangent modulus) on the residual stress profile in Si near isolated TSVs and linear TSV arrays. The results show that the magnitude and extent of the TSV-induced stress field in Si is a non-monotonic function of Cu yield stress. Moreover, the tensile or compressive nature of TSV-induced stress within and outside linear TSV arrays is also a strong function of the Cu yield stress. The simulated impact of Cu tangent modulus on TSV-induced stress in Si is less substantial. The implications of these results for TSV layout with respect to active device placement in a 3D system are discussed.