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Symmetry Measure for Memory Test and Its Application in BIST Optimization

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Abstract

Programmable Built-in Self-Test (BIST) has been widely used for testing embedded memories. The main disadvantage of having programmability on BIST circuits is the size of Test Algorithm Register (TAR) that becomes very crucial in case of complex test algorithms. To optimize Programmable BIST hardware symmetric March tests are usually used in BIST engines. On the other hand, the used definitions do not reflect completely the existing symmetry in test algorithms and they also do not reflect the fact that the level of symmetry in a given test algorithm can be measured. A new method of symmetry measurement for memory test algorithms and a corresponding metric are introduced. A dependency between symmetry measure and BIST optimization range is analyzed. Optimization experiments that have been done for a number of well-known test algorithms show that the BIST hardware gain could reach 48%. However, the time overhead is negligible in comparison with the hardware gain. The experiments also show that starting from some point a monotone dependency between symmetry measure and BIST hardware area exists.

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Authors and Affiliations

  1. Synopsys, 15/1 Khorenatsi str., Yerevan, Armenia, 0010

    Gurgen Harutyunyan, Aram Hakhumyan, Samvel Shoukourian & Valery A. Vardanian

  2. Synopsys, 700 East Middlefield Rd., Mountain View, CA, 94043, USA

    Yervant Zorian

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  1. Gurgen Harutyunyan
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  2. Aram Hakhumyan
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  3. Samvel Shoukourian
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  4. Valery A. Vardanian
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  5. Yervant Zorian
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Correspondence to Gurgen Harutyunyan.

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Responsible Editor: C. A. Papachristou

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Harutyunyan, G., Hakhumyan, A., Shoukourian, S. et al. Symmetry Measure for Memory Test and Its Application in BIST Optimization. J Electron Test 27, 753–766 (2011). https://doi.org/10.1007/s10836-011-5251-6

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  • DOI: https://doi.org/10.1007/s10836-011-5251-6

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