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An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture

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Abstract

Test data compression is an effective methodology for reducing test data volume and testing time. A novel compatibility-based test data compression method is presented in this paper. With the high compression efficiency of extended frequency-directed run length coding algorithm, the proposed method groups the test vectors that have least incompatible bits and amalgamates them into a single vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Three runs of 1, 0 and c can be encoded simultaneously. In addition, the corresponding decoder architecture with low hardware overhead has been developed. To evaluate the effectiveness of the proposed approach, in experiments, it is applied to the International Symposium on Circuits and Systems’ benchmark circuits. The experiments results show that the proposed algorithm gets a higher compression ratio than the conventional algorithms.

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Authors and Affiliations

  1. Institute of VlSI Design, Zhejiang University, P.O. Box 1713, YUQUAN Campus, Hangzhou, Zhejiang Province, 310027, China

    Min-yong Wan, Yong Ding, Yun Pan & Xiao-lang Yan

Authors
  1. Min-yong Wan
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  2. Yong Ding
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  3. Yun Pan
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  4. Xiao-lang Yan
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Corresponding author

Correspondence to Yong Ding.

Additional information

Responsible Editor: N. A. Touba

This research is supported by the National High Technology Research and Development Program of China (Grant No. 2009AA011706) and the Fundamental Research Funds for the Central Universities (Grant No. KYJD09012).

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Wan, My., Ding, Y., Pan, Y. et al. An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture. J Electron Test 27, 787–796 (2011). https://doi.org/10.1007/s10836-011-5258-z

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