On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs

Abstract

3D integration of ICs is an emerging technology where multiple silicon dies are stacked vertically. The manufacturing itself is based on wafer-to-wafer bonding, die-to-wafer bonding or die-to-die bonding. Wafer-to-wafer bonding has the lowest yield as a good die may be stacked against a bad die, resulting in a wasted good die. Thus the latter two options are preferred to keep yield high and manufacturing costs low. However, these methods require dies to be tested separately before they are stacked. A problem with testing dies separately is that the clock network of a prebond die may be incomplete before stacking. In this paper we present a solution to address this problem. The solution is based on on-die Delay Lock Loop (DLL) implementations that are only activated during testing prebond unstacked dies to synchronize disconnected clock regions. A problem with using DLLs in testing is that they cannot be turned on or off within a single cycle. Since scan-based testing requires that test patterns be scanned in at a slow clock frequency before fast capture clocks are applied, On-Product Clock Generation (OPCG) must be used. The proposed solution addresses the above problems and allows a prebond with an incomplete clock network to be tested with low skew.