Skip to main content
SpringerLink
Log in

Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper provides a new test technique for detecting defects in Through Silicon Via (TSV) in 3-D ICs and presents a substrate-dependent equivalent electrical model for TSVs. Process-related defects that affect the functional electrical performance of the TSV are identified, and fault models are developed for each individual defect. The fault models are integrated into the equivalent electrical model of the TSV for testing. Our test technique uses an RF carrier signal modulated with a multi-tone signal with added Gaussian white noise to synthesize the test stimulus; the peak-to-average ratio is measured as output response. We find a significant difference in peak-to-average ratio between defect-free and defective TSVs. Our test technique is very sensitive to small defects in these nanostructures, thereby identifying the defects with high accuracy.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Benabe E (1998) Automated characterization of ceramic multi-layer capacitors. In 52nd Advanced RF Techniques Group Conference, pp. 88–94

  2. Bermond C, Cadix L, Farcy A, Lacrevaz T, Leduc P, Flechet B (2009) High frequency characterization and modeling of high density TSV in 3D integrated circuits. 13th Workshop on Signal Propagation on Interconnects

  3. Chen H, Shih JY, Li SW, Lin HC, Wang MJ, Peng CN (2010) Electrical tests for three-dimensional ICs with TSVs. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  4. Chen PY, Wu CW, Kwai DM (2009) On-chip TSV testing for 3D IC before bonding using sense amplification. Proceedings of IEEE Asian Test Symposium

  5. Friese M (1997) Multitone signal with low crest factor. IEEE Transactions on Communications 45(10)

  6. Gupta A, Kannan S, Kim B (2010) Development of novel carbon nanotube TSV technology. Proceedings of 60th Electronic Components and Technologies Conference

  7. Kannan S, Kim B (2010) New testing technique for copper TSV in 60GHz wireless applications. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  8. Kannan S, Kim B, Evana SS, Gupta A, Li L (2011) 3-D copper-based TSV for 60-GHz applications. Proceedings of the 61st Electronic Components and Technologies Conference

  9. Kannan S, Kim B, Srinivasan G, Taenzlar F, Antley R, Force C (2011) Embedded RF circuit diagnostic technique with multi-tone dither scheme. Journal of Electronic Testing Theory and Applications 27

  10. Kikuchi H (2008) Tungsten through-silicon via technology for three dimensional LSIs. Journal of Applied Physics 47:2801–2806

    Article  Google Scholar 

  11. Kim B, Chatterjee A, Swaminathan M, Schimmel D (1994) A novel low-cost approach to MCM interconnect test. In Proceedings of IEEE International Test Conference, pp. 184–192

  12. Lakshminarayanan B, Gordon HC Jr., Weller TM (2000) A substrate-dependent CAD model for ceramic multilayer capacitors. IEEE Transactions on Microwave Theory and Techniques 48(10)

  13. Lim SK (2010) TSV-aware 3D physical design tool needs for faster mainstream acceptance of 3D ICs. ACM Design Automation Conference

  14. Lim SK (2010) 3D circuit design with through-silicon-via: Challenges and opportunities. IEEE Electronic Design Processes Symposium Workshop

  15. Liu X, Chen Q, Dixit P, Chatterjee R, Tummala RR, Sitaraman SK (2009) Failure mechanisms and optimum design for electroplated copper through-silicon vias. Proceedings of the 58th Electronic Components and Technologies Conference

  16. Lou Y, Yan Z, Zhang F, Franzon PD (2010) Comparing through-silicon-via (TSV) void/pinhole defect self-test methods. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  17. Maher JP, Jacobsen RT, Laferty RE (1978) High-frequency measurements of Q-factors of ceramic chip capacitors. IEEE Transactions on Components, Hybrids Manufacturing Technology CHMT-1:257–264

    Article  Google Scholar 

  18. Ozkan U, Nied HF (2008) Finite element based three dimensional crack propagation simulation on interfaces in electronic packages. Proceedings of the 58th Electronic Components and Technologies Conference

  19. Pavlidis VF, Friedman EG (2009) Three-dimensional integrated circuit design. Morgan Kauffmann, Burlington, pp 35–65

    Google Scholar 

  20. Pucel RA (1981) Design considerations for monolithic microwave circuits. IEEE Transaction on Microwave Theory and Techniques MTT-29:513–534

    Article  Google Scholar 

  21. Ryu C, Lee J, Lee H, Lee K, Oh T, Kim J (2006) High frequency electrical model of through wafer via for 3-D stacked chip packaging. Electronics System Integration Technology Conference

  22. Shen H, Shih JY, Li SW, Lin HC, Wang MJ, Peng CN (2010) Electrical tests for three-dimensional ICs with TSVs. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  23. Sih GC, Zuo JZ (2000) Multiscale behavior of crack initiation and growth in piezoelectric ceramics. Theoretical and Applied Fracture Mechanics 34

  24. Steinhogl W, Schindler G, Steinlesberger G, Traving M, Engelhardt M (2005) Comprehensive study of the resistivity of copper wires with lateral dimensions 100 nm and smaller. Journal of Applied Physics 97(2):023706-1–023706-7

    Article  Google Scholar 

  25. Sukharev V, Kteyan A, Khachatryan N, Hovsepyan H, Choy JH, Zschech E, Huebner R (2010) Multi-scale simulation and characterization for stress management in 3D IC TSV-based integration technology: stress assessment for chip performance. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  26. Taneja S, Keller B (2010) An integrated approach to design and test 3-D chips. International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

  27. Tsai M, Klooz A, Leonard A, Appel J, Franzon P (2009) Through silicon-via (TSV) void/pinhole defect self-test circuit for 3D-IC. Proceedings of IEEE International Conference on 3D System Integration

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, The University of Alabama, Tuscaloosa, AL, USA

    Sukeshwar Kannan & Bruce Kim

  2. Yeungnam University, Gyeongsan, South Korea

    Byoungchul Ahn

Authors
  1. Sukeshwar Kannan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Bruce Kim
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Byoungchul Ahn
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sukeshwar Kannan.

Additional information

Responsible Editor: E.J. Marinissen

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kannan, S., Kim, B. & Ahn, B. Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects. J Electron Test 28, 39–51 (2012). https://doi.org/10.1007/s10836-011-5263-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5263-2

Keywords

Search

Navigation