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A New Optimal Test Node Selection Method for Analog Circuit

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Abstract

The existing test node selection methods of analog dictionary technique assume that the voltage gap of ambiguity group is 0.7 V. However, this technique is not always accurate to determine the right ambiguity gap for each fault mode. As the probability density of the circuit output approximately satisfies the normal distribution, an accurate technique is introduced to determine the ambiguity gap. Then, this paper proposes a new test node selection method with an extended fault dictionary and the overlapped area values. Firstly, the fault dictionary is constructed with the mean and standard variance values of node voltage. Then, the area detection table is generated by the overlapped area values under normal curves for ambiguity faults, which represent the failure probability of ambiguity faults. Finally, the optimal test node set is selected by fusing fault isolation and overlapped area information. The results show that the proposed method is effective to select the optimal test node set and improve the performance of analog fault diagnosis.

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Acknowledgments

This work is supported by National Natural Science Foundation of China (No. 60871009), Aviation Science Foundation of China (No.2011ZD52050), Funding of Jiangsu Innovation Program for Graduate Education (No.CX10B_098Z). The authors are grateful for editors and anonymous reviewers who make constructive comments.

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Authors and Affiliations

  1. College of Automation Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, Jiangsu Province, People’s Republic of China

    Hui Luo, Youren Wang & Hua Lin

  2. College of Electric and Information Engineering, Anhui University of Science and Technology, Huainan, 232001, Anhui Province, People’s Republic of China

    Yuanyuan Jiang

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  1. Hui Luo
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  2. Youren Wang
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  3. Hua Lin
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  4. Yuanyuan Jiang
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Correspondence to Hui Luo.

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Responsible Editor: R. A. Parekhji

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Luo, H., Wang, Y., Lin, H. et al. A New Optimal Test Node Selection Method for Analog Circuit. J Electron Test 28, 279–290 (2012). https://doi.org/10.1007/s10836-011-5274-z

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  • DOI: https://doi.org/10.1007/s10836-011-5274-z

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