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Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories

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Abstract

The embedded Flash (eFlash) technology can be subject to defects creating functional faults. In this paper, we first generalize the electrical model of the ATMEL TSTAC™ eFlash memory technology proposed in [10]. The model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model is validated by means of simulations and comparisons with ATMEL silicon data. Then, we present a complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC™ eFlash array by considering the proposed model on a hypothetical 4 × 4 array. This analysis highlights the interest of the proposed model to provide a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing.

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Authors and Affiliations

  1. Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, 161, rue Ada, 34392, Montpellier Cedex 5, France

    P.-D. Mauroux, A. Virazel, A. Bosio, L. Dilillo, P. Girard & S. Pravossoudovitch

  2. ATMEL Rousset—Libraries and Design Tools Department, Embedded Non-Volatile Memory Group, 13106, Rousset Cedex, France

    B. Godard, G. Festes & L. Vachez

Authors
  1. P.-D. Mauroux
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  2. A. Virazel
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  3. A. Bosio
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  4. L. Dilillo
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  5. P. Girard
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  6. S. Pravossoudovitch
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  7. B. Godard
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  8. G. Festes
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  9. L. Vachez
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Corresponding author

Correspondence to A. Virazel.

Additional information

Responsible Editor: C. A. Papachristou

This paper is an extended version of a previously published paper. Main contributions of this paper with respect to [10] are:

-A generalization of the model initially proposed in [10] to the case of multiple word-lines, -A complete analysis of actual resistive defects (open and short) that may affect the ATMEL TSTAC/ eFlash array, -A fault modeling of actual resistive defect injection.

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Mauroux, PD., Virazel, A., Bosio, A. et al. Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories. J Electron Test 28, 215–228 (2012). https://doi.org/10.1007/s10836-012-5277-4

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  • DOI: https://doi.org/10.1007/s10836-012-5277-4

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