Skip to main content
Log in

Diagnostic Test Set Minimization and Full-Response Fault Dictionary

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

We minimize a given test set without loss of diagnostic resolution in full-response fault dictionary. An integer linear program (ILP), formulated from fault simulation data, provides ultimate reduction of test vectors while preserving fault coverage and pair-wise distinguishability of faults. The complexity of the ILP is made manageable by two innovations. First, we define a generalized independence relation between pairs of faults to reduce the number of fault pairs that need to be distinguished. This significantly reduces the number of ILP constraints. Second, we propose a two-phase ILP approach. In the first phase, using an existing procedure, we select a minimal detection test set. In the second phase, additional tests are selected for the undiagnosed faults using a newly formulated diagnostic ILP. The overall minimized test set may be only slightly longer than a one-step ILP optimization, but has advantages of reducing the minimization problem complexity and the test time required by the minimized tests. Benchmark results show potential for significantly smaller diagnostic test sets.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2

Similar content being viewed by others

References

  1. Abramovici M, Breuer MA (1980) Multiple fault diagnosis in combinational circuits based on an effect-cause analysis. IEEE Trans Comput C-29(6):451–460

    Article  MathSciNet  Google Scholar 

  2. Agrawal VD, Baik DH, Kim YC, Saluja KK (2003) Exclusive test and its applications to fault diagnosis. In: Proc. 16th international conf. VLSI design, pp 143–148

  3. Aitken RC, Maxwell PC (1995) Better models or better algorithms? On techniques to improve fault diagnosis. Hewlett-Packard J 46(1):110–116

    Google Scholar 

  4. Akers SB, Joseph C, Krishnamurthy B (1987) On the role of independent fault sets in the generation of minimal test sets. In: Proc. international test conf., pp 1100–1107

  5. Boppana V, Fuchs WK (1994) Fault dictionary compression by output sequence removal. In: Proc. international conf. computer-aided design, pp 576–579

  6. Boppana V, Hartanto I, Fuchs WK (1996) Full fault dictionary storage based on labeled tree encoding. In: Proc. 14th IEEE VLSI test symp., pp 174–179

  7. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory & mixed-signal VLSI circuits. Springer, Boston

    Google Scholar 

  8. Chess B (1995) Diagnostic test pattern generation and the creation of small fault dictionaries. Master’s thesis, University of California, Santa Cruz, Computer Engineering

  9. Chess B, Larrabee T (1999) Creating small fault dictionaries. IEEE Trans Comput-Aided Des 18(3):346–356

    Article  Google Scholar 

  10. Drineas P, Makris Y (2003) Test sequence compaction through integer programming. In: Proc. international conf. computer design, pp 380–386

  11. Flores PF, Neto HC, Marques Silva JP (2001) An exact solution to the minimum size test pattern problem. ACM Transact Des Automat Electron Syst 6(4):629–644

    Article  Google Scholar 

  12. Fourer R, Gay DM, Kernighan BW (2003) AMPL: a mathematical programming language. Brooks/Cole-Thomson Learning

  13. Higami Y, Saluja KK, Takahashi H, Kobayashi S, Takamatsu Y (2006) Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. In: Proc. asia and south pacific design automation conf., pp 75–80

  14. Kantipudi KR, Agrawal VD (2006) On the size and generation of minimal N-detection tests. In: Proc. 19th int. conf. VLSI design, pp 425–430

  15. Kantipudi KR, Agrawal VD (2007) A reduced complexity algorithm for minimizing N-detect tests. In: Proc. 20th int. conf. VLSI design, pp 492–497

  16. Lavo D, Chess B, Larrabee T, Ferguson FJ (1998) Diagnosing realistic bridging faults with single stuck-at information. IEEE Trans Comput-Aided Des 17(3):255–268

    Article  Google Scholar 

  17. Lavo D, Larrabee T (2001) Making cause-effect cost effective: low-resolution fault dictionaries. In: Proc. international test conf., pp 278–286

  18. Lee HK, Ha DS (1993) On the generation of test patterns for combinational circuits. Tech. Report 12-93, Dept. of Elec. Eng., Virginia Polytechnic Institute and State University, Blacksburg, Virginia

  19. Lee HK, Ha DS (1996) HOPE: an effcient parallel fault simulator for synchronous sequential circuits. IEEE Trans Comput-Aided Des 15(9):1048–1058

    Article  Google Scholar 

  20. Lin Y-C, Cheng K-T (2006) Multiple-fault diagnosis based on single-fault activation and single-output observation. In: Proc. design, automation and test in Europe (DATE), pp 424–429

  21. Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. In: Proc. international conf. computer-aided design, pp 272–278

  22. Shukoor MA (2009) Fault detection and diagnostic test set minimization. Master’s thesis, Auburn University, ECE Department

  23. Shukoor MA, Agrawal VD (2008) A primal-dual solution to the minimal test generation problem. In: Proc. 12th VLSI design and test symp., pp 169–179

  24. Shukoor MA, Agrawal VD (2009) A two phase approach for minimal diagnostic test set generation. In: Proc. 14th IEEE European test symp., pp 115–120

  25. Shukoor MA, Agrawal VD (2009) Compaction of diagnostic test set for a full-response dictionary. In: Proc. 18th IEEE north atlantic test workshop, pp 104–111

  26. Strang G (1988) Linear algebra and its applications, 3rd edn. Harcourt Brace Javanovich College Publishers, Fort Worth

    Google Scholar 

  27. Veneris A, Chang R, Abadir MS, Amiri M (2004) Fault equivalence and diagnostic test generation using ATPG. In: Proc. international symp. circuits and systems, pp 221–224

  28. Venkataraman S, Hartanto I, Fuchs WK (1996) Dynamic diagnosis of sequential circuits. In: Proc. 14th IEEE VLSI test symp., pp 198–203

  29. Yogi N, Agrawal VD (2008) N-model tests for VLSI circuits. In: Proc. 40th southeastern symp. system theory, pp 242–246

  30. Zhang Y, Agrawal VD (2010) A diagnostic test generation system. In: Proc. international test conf. Paper 12.3

  31. Zhang Y, Agrawal VD (2011) Reduced complexity test generation algorithms for transition fault diagnosis. In: Proc. 29th conf. computer design, pp 96–101

  32. Zhao L, Agrawal VD (2012) Net diagnosis using stuck-at and transition fault models. In: Proc. 30th IEEE VLSI test symp.

Download references

Acknowledgements

This research was supported in part by the National Science Foundation Grant CNS-0708962 and the Wireless Engineering Research and Education Center (WEREC), Auburn University, Auburn, AL 36849, USA. This work was first presented at the 14th IEEE European Test Symposium in 2009.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Vishwani D. Agrawal.

Additional information

Responsible Editor: C. Metra

Rights and permissions

Reprints and permissions

About this article

Cite this article

Shukoor, M.A., Agrawal, V.D. Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J Electron Test 28, 177–187 (2012). https://doi.org/10.1007/s10836-012-5286-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-012-5286-3

Keywords

Navigation