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Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits

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Abstract

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variation models to estimate the effect of Process, power supply Voltage, and Temperature (PVT) variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of circuits designed in 65, 45, and 32 nm CMOS technologies are presented demonstrating that the models can be used for the analytical derivation of delay variability windows and delay variability statistical distributions associated to process variations. This information can be used during the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of PVT variations to be assessed in the design environment. On the other hand, it allows boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits’ performance can simultaneously be analyzed with those of power supply voltage and temperature variations. Experimental results have also been obtained on several FPGA boards including nanometer-scale Xilinx™ and Altera™ devices. These results provide a proof-of-concept, on real circuits, of the practical usefulness of the models.

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Acknowledgments

This research was partially supported under Spanish TEC2010-21429-C02-01 project and ENIAC SE2A Project, and also by Portuguese FCT (INESC-ID multiannual funding) through the PIDDAC Program.

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Authors and Affiliations

  1. Department of Electronic Technology, University of Vigo, Campus Universitario, 36310, Vigo, Spain

    Judit F. Freijedo & Juan J. Rodriguez-Andina

  2. Engineering Institute, Univ. of Algarve, Campus da Penha, 8005-139, Faro, Portugal

    Jorge Semião

  3. Electrical Engineering Department, Catholic University – PUCRS, Av. Ipiranga, 6681, 90619-900, Porto Alegre, Brazil

    Fabian Vargas

  4. IST, Technical University of Lisbon/INESC-ID, Rua Alves Redol, 9, 1000-029, Lisbon, Portugal

    Isabel C. Teixeira & J. Paulo Teixeira

Authors
  1. Judit F. Freijedo
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  2. Jorge Semião
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Correspondence to Juan J. Rodriguez-Andina.

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Freijedo, J.F., Semião, J., Rodriguez-Andina, J.J. et al. Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. J Electron Test 28, 421–434 (2012). https://doi.org/10.1007/s10836-012-5297-0

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  • DOI: https://doi.org/10.1007/s10836-012-5297-0

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