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Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits

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Abstract

The implementation of complex, high-performance digital functionality in nanometer CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper proposes the application of unified semi-empirical propagation delay variation models to estimate the effect of Process, power supply Voltage, and Temperature (PVT) variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of circuits designed in 65, 45, and 32 nm CMOS technologies are presented demonstrating that the models can be used for the analytical derivation of delay variability windows and delay variability statistical distributions associated to process variations. This information can be used during the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of PVT variations to be assessed in the design environment. On the other hand, it allows boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits’ performance can simultaneously be analyzed with those of power supply voltage and temperature variations. Experimental results have also been obtained on several FPGA boards including nanometer-scale Xilinx™ and Altera™ devices. These results provide a proof-of-concept, on real circuits, of the practical usefulness of the models.

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References

  1. Agarwal A, Dartu F, Blaauw D. “Statistical gate delay model considering multiple input switching”, Proc. DAC’04, pp. 658–663

  2. Ajami AH, Banerjee K, Pedram M (2005) Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans CAD 24:849–861

    Google Scholar 

  3. Alioto M, Palumbo G, Pennisi M (2010) Understanding the effect of process variations on the delay of static and domino logic. IEEE Trans VLSI Syst 18:697–710

    Article  Google Scholar 

  4. ARM/IEM, http://www.arm.com/products/esd/iem_home.html

  5. Barros Júnior D, Rodríguez-Irago M, Santos MB, Teixeira IC, Vargas F, Teixeira JP (2005) Fault modeling and simulation of power supply voltage transients in digital Systems on a Chip. J Electron Test Theor Appl (JETTA) 21:349–363

    Article  Google Scholar 

  6. Bowman KA, Tschanz J, Wilkerson Ch, Lu S-L, Karnik T, De V, Borkar SY. “Circuit techniques for dynamic variation tolerance”, Proc. DAC’09, pp.4–7

  7. Bowman KA, Tschanz J, Kim NS, Lee JC, Wilkerson Ch, Lu S-L, Karnik T, De V, Borkar SY (2009) Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE J Solid State Circuits 44:49–63

    Article  Google Scholar 

  8. Chakraborty A, Duraisami K, Sathanur A, Sithambaram P, Benini L, Macii A, Macii E, Poncino M. “Dynamic thermal clock skew compensation using tunable delay buffers”. Proc. ISLPED’06, pp.162–167

  9. Cheng L, Xiong J, He L (2009) Non-gaussian statistical timing analysis using second-order polynomial fitting. IEEE Trans CAD 28:130–140

    Google Scholar 

  10. FARADAY UMC 130nm Cell Library, “FSC0H_D_ Databook_v1.1”, FSC0H_D 0.13um Standard Cell, 2004

  11. Flynn J (2004) “Power management in complex SoC design”, Synopsys White Paper, http://www.synopsys.com/sps, April

  12. Freijedo J, Semião J, Rodriguez-Andina JJ, Vargas F, Teixeira IC, Teixeira JP. “An accurate path delay model for multi-VDD dynamic testing of digital circuits”, Proc. LATW’08, pp. 23–28

  13. Freijedo J, Costas L, Semião J, Rodríguez-Andina JJ, Moure MJ, Vargas F, Teixeira IC, Teixeira JP (2010) Impact of power supply voltage variations on FPGA-based digital systems performance. J Low Power Electron 6:339–349

    Article  Google Scholar 

  14. Freijedo J, Semião J, Rodríguez-Andina JJ, Vargas F, Teixeira IC, Teixeira JP (2008) Delay modeling for power noise- and temperature-aware design and test of digital systems. J Low Power Electron 4:385–391

    Article  Google Scholar 

  15. Freijedo J, Valdés M, Costas L, Moure MJ, Rodríguez-Andina JJ, Semião J, Vargas F, Teixeira IC, Teixeira JP (2011) Lower VDD operation of FPGA-based digital circuits through delay modeling and time borrowing. J Low Power Electron 7:185–198

    Article  Google Scholar 

  16. Harish BP, Bhat N, Patil MB (2007) On a generalized framework for modeling the effects of process variations on circuit delay performance using response surface methodology. IEEE Trans CAD 26:606–614

    Google Scholar 

  17. IBM PowerPC, http://www.chips.ibm.com/products/powerpc/

  18. Jaffari J, Anis M (2008) Statistical thermal profile considering process variations: analysis and applications. IEEE Trans CAD 27:1027–1040

    Google Scholar 

  19. Lin Y, He L, Hutton M (2008) Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs. IEEE Trans VLSI Syst 16:124–133

    Article  Google Scholar 

  20. Mentor Graphics White Paper, “Design for variability: Managing design, process, and manufacturing variations in physical design”, http://www.mentor.com/resources/techpubs/upload/mentorpaper_43548.pdf, Oct. 2008

  21. Mitra S, Brelsford K, Kim YM, Lee H-HK, Li Y (2011) Robust system design to overcome CMOS reliability challenges. IEEE J Emerging and Selected Topics in Circuits and Systems 1:30–41

    Article  Google Scholar 

  22. Nabaa G, Azizi N, Najm FN. “An adaptive FPGA architecture with process variation compensation and reduced leakage”, Proc. DAC’06, pp. 624–629

  23. Nourani M, Attarha A (2002) Signal integrity: fault modeling and testing in high-speed SoCs. J Electron Test Theor Appl (JETTA) 18:539–554

    Article  Google Scholar 

  24. Oliveira R, Semião J, Teixeira I, Santos M, Teixeira P. "On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications", Proc. LATW'11

  25. Orshansky M, Keutzer K. “A general probabilistic framework for worst-case timing analysis”, Proc. DAC’02, pp. 556–561

  26. Pering T, Burd T, Brodersen R. “The simulation and evaluation of Dynamic Voltage Scaling algorithms.” Proc. ISLPED’98, pp. 76–81

  27. Reda S, Nassif SR. “Analyzing the impact of process variations on parametric measurements: Novel models and applications”, Proc. DATE’09, pp. 375–380

  28. Rodríguez-Irago M, Rodríguez Andina JJ, Vargas F, Semião J, Teixeira IC, Teixeira JP. “Dynamic fault detection in digital systems using Dynamic Voltage Scaling and multi-temperature schemes", Proc. IOLTS’06

  29. Rodríguez-Irago M, Rodríguez Andina JJ, Vargas F, Teixeira IC, Teixeira JP. “On the use of multi-clock, multi-VDD and multi-temperature schemes to improve dynamic fault detection in digital systems”, Proc. ETS’06, Informal Digest

  30. Rodríguez-Irago M, Rodríguez-Andina JJ, Barros Júnior D, Vargas F, Santos MB, Teixeira IC, Teixeira JP. “Using multiple clock schemes and multi-VDD test for dynamic fault detection in digital systems”, Proc. LATW’05, pp. 87–92

  31. Rodríguez-Irago M, Rodríguez-Andina JJ, Vargas F, Teixeira IC, Teixeira JP. “Using multiple-clock schemes and multi-T test for dynamic fault detection in digital systems”, Proc. LATW’06, pp. 103–107

  32. Rodríguez-Irago M, Semião J, Rodríguez-Andina JJ, Vargas F, Teixeira IC, Teixeira JP. “A model for the analytical definition of multi-VDD, multi-T dynamic tests in nanometer digital circuits”, Proc. LATW’07, pp. 55–60

  33. Sakurai T, Newton A (1990) Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas. IEEE J Solid State Circuits 25:584–594

    Article  Google Scholar 

  34. Salzmann J, Sill F, Timmermann D (2007) “Algorithm for Fast Statistical Timing Analysis”, Proc. International Symposium on System-on-Chip, pp. 90–93

  35. Semião J, Freijedo J, Rodriguez-Andina J, Vargas F, Santos M, Teixeira I, Teixeira P. “Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies”, Proc. IOLTS’09, pp. 223–228

  36. Transmeta Crusoe. http://www.transmeta.com/technology/index.html

  37. Visweswariah C (2004) “Statistical analysis and design: From picoseconds to probabilities”, Proc. 17th Symposium on Integrated Circuits and System Design

  38. Wang J, Walker DMH, Majhi A, Kruseman B, Gronthoud G, Villagra LE, van de Wiel P, Eichenberger S. “Power supply noise in delay testing”, Proc. ITC’06

  39. Zhang Y, Dick R, Chakrabarty K. “Energy-aware deterministic fault tolerance in distributed real-time embedded systems”, Proc. DAC’04, pp. 550–554

  40. Zhao W, Cao Y. “Predictive technology model for nano-CMOS design exploration”, ACM J. Emerging Technologies in Computing Systems, vol. 3, Apr. 2007 (models available at http://www.eas.asu.edu/~ptm/)

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Acknowledgments

This research was partially supported under Spanish TEC2010-21429-C02-01 project and ENIAC SE2A Project, and also by Portuguese FCT (INESC-ID multiannual funding) through the PIDDAC Program.

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Authors and Affiliations

  1. Department of Electronic Technology, University of Vigo, Campus Universitario, 36310, Vigo, Spain

    Judit F. Freijedo & Juan J. Rodriguez-Andina

  2. Engineering Institute, Univ. of Algarve, Campus da Penha, 8005-139, Faro, Portugal

    Jorge Semião

  3. Electrical Engineering Department, Catholic University – PUCRS, Av. Ipiranga, 6681, 90619-900, Porto Alegre, Brazil

    Fabian Vargas

  4. IST, Technical University of Lisbon/INESC-ID, Rua Alves Redol, 9, 1000-029, Lisbon, Portugal

    Isabel C. Teixeira & J. Paulo Teixeira

Authors
  1. Judit F. Freijedo
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  2. Jorge Semião
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  3. Juan J. Rodriguez-Andina
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  4. Fabian Vargas
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  5. Isabel C. Teixeira
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  6. J. Paulo Teixeira
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Correspondence to Juan J. Rodriguez-Andina.

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Responsible Editor: V. Champac

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Freijedo, J.F., Semião, J., Rodriguez-Andina, J.J. et al. Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. J Electron Test 28, 421–434 (2012). https://doi.org/10.1007/s10836-012-5297-0

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  • DOI: https://doi.org/10.1007/s10836-012-5297-0

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