Abstract
The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.
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Acknowledgments
The work has been supported by European Commission Framework Program 7 project FP7-ICT-2009-4-248613 DIAMOND, by Research Centre CEBE funded by European Union through the European Structural Funds and by Estonian Science Foundation grants 9429 and 8478.
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Viilukas, T., Karputkin, A., Raik, J. et al. Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J Electron Test 28, 511–521 (2012). https://doi.org/10.1007/s10836-012-5312-5
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DOI: https://doi.org/10.1007/s10836-012-5312-5