Abstract
Testing of ADCs deeply embedded in SOCs is a significant challenge due to access limitations. ADC Built-in self-test (BIST) is considered a promising alternative to traditional test. This paper investigates implementation issues in adapting the stimulus error identification and removal (SEIR) algorithm, originally developed for production test, into a practical ADC BIST solution. Signal generators with very low transistor count and area consumption are presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that the generated signals, together with the level shifts, are able to test a 16-bit ADC to 16 bit accuracy levels. These results demonstrate that accurate BIST of deeply embedded analog and mixed-signal (AMS) blocks may be practically implemented on chip with very low overhead.
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Duan, J., Vasan, B., Zhao, C. et al. On Chip Signal Generators for Low Overhead ADC BIST. J Electron Test 28, 615–623 (2012). https://doi.org/10.1007/s10836-012-5320-5
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DOI: https://doi.org/10.1007/s10836-012-5320-5