Skip to main content
SpringerLink
Log in

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Bernstein K, Andry P, Cann J et al (2007) Interconnects in the third dimension: design challenges for 3D ICs. Proceedings of the 44th Design Automation Conference, pp 562–567

  2. Cuviello M, Dey S, Bai X, Zhao Y (1999) Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects. Proceedings of International Conference on Computer-Aided Design (ICCAD), pp 297–303

  3. Emma PG, Kursur E et al (2008) Is 3D chip technology the next growth engine for performance improvement? IBM J Res Dev 52(6)

  4. Frank T, Frank T, Chappaz C et al (2010) Reliability approach of high density Through Silicon Via (TSV). Proceedings of 12th Electronics Packaging Technology Conference (EPTC), pp 312–324

  5. Goel P, McMahon MT (1982) Electronic Chip-in-Place Test. Proceedings of International Test Conference (ITC), pp 83–90

  6. Grange M, Weerasekera R, Pamunuwa D, Tenhunen H (2009) Examination of delay and signal integrity metrics in through silicon vias. Proceedings of 3D Integration Workshop, Design Automation and Test in Europe Conference(DATE), pp 89–92

  7. Huang Y-J, Li J-F, Chen J-J, Kwai D-M, Chou Y-F, Wu C-W (2011) A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. Proceedings of VLSI Test Symposium (VTS), pp 20–25

  8. Jarwala N, Yau CW (1989) A new framework for analyzing test generation and diagnosis algorithms for board interconnects. Proceedings of International Test Conference (ITC), pp 63–70

  9. Jutman A (2004) At-speed on-chip diagnosis of board-level interconnect faults. Proceedings of European Test Symposium (ETS), pp 2–7

  10. Karmarkar AP, Xu XX, Moroz V (2009) Performanace and reliability analysis of 3D-integration structures employing Through Silicon Via (TSV). Proceedings of International Reliability Physics Symposium (IRPS), pp 682–687

  11. Kautz WH (1974) Testing of faults in wiring interconnects. IEEE Trans Comput 23(4):358–363

    Article  MATH  Google Scholar 

  12. Leduc P, de Crecy F, Fayolle M, Charlet B, Enot T, Zussy M et al (2007) Challenges for 3D IC integration: bonding quality and thermal management. Proceedings of the IEEE International Interconnect Technology Conference (IITC), pp 210–212

  13. Lee H-HS, Chakrabarty K (2009) Test challenges for 3D integrated circuits. IEEE Des Test Comput 26(5):26–35

    Article  Google Scholar 

  14. Liu X, Chen O, Dixit P, Chatterjee R, Tummala RR, Sitaraman SK (2009) Failure mechanisms and optimum design for electroplated copper Through-Silicon Vias (TSV). Proceeding of 59th Electronic Components and Technology Conference (ECTC), pp 624–629

  15. Liu C, Song T, Cho J, Kim J, Kim J, Lim SK (2011) Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. Proceedings of the Design Automation Conference (DAC), pp 783–788

  16. Liu C, Song T, Lim SK (2011) Signal integrity analysis and optimization for 3D ICs. Proceedings of International Symposyum on Quality Electronic Design (ISQED), pp 42–49

  17. Loi I, Angiolini F, Benini L (2008) Developing mesochronous synchronizers to enable 3D NoCs. Proceedings of the Conference on Design, Automation and Test in Europe (DATE), pp 1414–1419

  18. Marinissen EJ (2010) Testing TSV-based three-dimensional stacked ICs. Proceedings of Design, Automation and Test in Europe (DATE) Conference, pp 1689–1694

  19. Marinissen EJ, Zorian Y (2009) Testing 3D chips containing through-silicon vias. Proceedings of International Test Conference (ITC), pp 1–11

  20. Patti R (2006) Three-dimensional integrated circuits and the future of System-on-Chip designs. Proc IEEE 84(6):1214–1224

    Article  Google Scholar 

  21. Pendurkar R, Chatterjee A, Zorian Y (2001) Switching activity generation with automated BIST synthesis for performance testing of interconnects. IEEE Trans Comput-Aid Des Integr Circ Syst (TCAD) 20(9):1143–1158

    Article  Google Scholar 

  22. Sekar K, Dey S (2002) LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects. Proceedings of VLSI Test Symposium (VTS), pp 417–422

  23. Topol AW et al (2006) Three-dimensional integrated circuits. IBM J Res Dev 50(4/5)

  24. Wagner PT (1987) Interconnect testing with boundary scan. Proceedings of International Test Conference (ITC), pp 52–57

Download references

Author information

Authors and Affiliations

  1. TIMA Laboratory (INP Grenoble, UJF, CNRS), Grenoble, France

    Vladimir Pasca, Lorena Anghel & Mounir Benabdenbi

Authors
  1. Vladimir Pasca
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Lorena Anghel
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mounir Benabdenbi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vladimir Pasca.

Additional information

Responsible Editor: V. Champac

Rights and permissions

Reprints and permissions

About this article

Cite this article

Pasca, V., Anghel, L. & Benabdenbi, M. Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis. J Electron Test 28, 817–829 (2012). https://doi.org/10.1007/s10836-012-5322-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-012-5322-3

Keywords

Search

Navigation