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An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

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Abstract

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.

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Authors and Affiliations

  1. Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, 31040, Taiwan

    Xuan-Lun Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou & Ding-Ming Kwai

  2. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 10617, Taiwan

    Jiun-Lang Huang

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  1. Xuan-Lun Huang
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  2. Jiun-Lang Huang
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  3. Hung-I Chen
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  4. Chang-Yu Chen
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  5. Tseng Kuo-Tsai
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  6. Ming-Feng Huang
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  7. Yung-Fa Chou
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  8. Ding-Ming Kwai
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Correspondence to Xuan-Lun Huang.

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Responsible Editor: D. Keezer

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Huang, XL., Huang, JL., Chen, HI. et al. An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J Electron Test 28, 705–722 (2012). https://doi.org/10.1007/s10836-012-5325-0

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  • DOI: https://doi.org/10.1007/s10836-012-5325-0

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