Skip to main content
SpringerLink
Log in

Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by fabrication errors. The fraction of defective chips that escapes to the customer is called the defect level, also known as defective parts per million (DPPM, or simply PPM) when normalized to one million units. This paper demonstrates a technique used to correlate coverage goals to DPPM based on test fallout data using a MATLAB®-based error function minimization approach. This analysis is explained using regression models for DPPM yield versus fault/defect coverage. This approach is beneficial to semiconductor companies for calibrating their fault coverage goals to meet DPPM requirements from automotive or other customers that have very aggressive (i.e., ultra-low) DPPM demands.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4

References

  1. Agrawal VD, Seth SC, Agrawal P (1982) Fault coverage requirement in production testing of LSI circuits. IEEE J Solid State Circuits 17(1):57–61

    Article  Google Scholar 

  2. Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer

  3. Butler KM, Carulli JM Jr, Saxena J, Nahar A, Daasch WR (2009) Multidimensional test escape rate modeling. IEEE Des Test Comput 26(5):74–82

    Article  Google Scholar 

  4. Chakraborty K (2010) “A MATLAB® based technique for defect level estimation using data mining of test fallout data versus fault coverage.” Proc. IEEE International Symposium on Quality Electronic Design (ISQED), pp. 418–421

  5. Hirase J, Hamada M (1994) “The effect of fault detection by IDDQ measurement for CMOS VLSIs.” Proc. Asian Test Symposum, pp. 144–149

  6. Marinissen EJ, Singh A, Glotter D, Esposito M, Carulli Jr. JM, Nahar A, Butler KM, Appello D, Portelli C (2010) “Adapting to adaptive testing.” Proc. Design Automation and Test in Europe Conference (DATE), pp. 556–561

  7. MATLAB® Online Reference Manual, www.mathworks.com, accessed on April 7, 2012

  8. McDonald CJ (1999) Tutorial paper: new tools for yield improvement in integrated circuit manufacturing: can they be applied to reliability? Microelectron Reliab (Elsevier) 39:731–739

    Article  Google Scholar 

  9. Mohanty A. Indian Institute of Science, Bangalore, India, personal communication on MATLAB® algorithms

  10. Murphy BT (1964) Cost-size optima of monolithic integrated circuits. Proc IEEE 52(12):1537–1545

    Article  Google Scholar 

  11. Seeds RB (1967) Yield, economic, and logistical models for complex digital arrays. IEEE Int Conv Rec Part 6, pp. 60–61

    Google Scholar 

  12. Spica M. Cypress Semiconductor, USA, personal communication on defect distribution and systematic defect coefficients in industrial wafers

  13. Stapper CH (1973) Defect density distribution for LSI yield calculations. IEEE Trans Electron Devices 20(7):655–657

    Article  Google Scholar 

  14. Stapper CH (1976) LSI yield modeling and process monitoring. IBM J Res Dev 20(3):228–234

    Article  Google Scholar 

  15. TurboFault (2010) Reference manual. SynTest Technologies, Sunnyvale

    Google Scholar 

  16. Walker DMH, Director SW (1986) VLASIC: a catastrophic fault yield simulator for integrated circuits. IEEE Trans Comput Aided Des Circ Syst CAD-5(4):541–556

    Article  Google Scholar 

  17. Williams TW, Brown NC (1981) Defect level as a function of fault coverage. IEEE Trans Comput C-30(12):987–988

    Article  Google Scholar 

  18. Zachariah ST, Chakravarty S (1999) A comparative study of pseudo stuck-at and leakage fault model. Proc. International Conference on VLSI Design, pp. 91–94

  19. Zhao G-N (1996) Analog design-for-testability for analog/mixed-signal ASICs. Proc. International Conference on ASIC, pp. 404–408

Download references

Acknowledgment

K. Chakraborty was formerly with Cypress Semiconductor, San Jose, California, where this work was performed.

Author information

Authors and Affiliations

  1. Lattice Semiconductor, Hillsboro, OR, 97124, USA

    Kanad Chakraborty

  2. Auburn University, Auburn, AL, 36849, USA

    Vishwani D. Agrawal

Authors
  1. Kanad Chakraborty
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vishwani D. Agrawal
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Kanad Chakraborty.

Additional information

Responsible Editor: K. K. Saluja

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chakraborty, K., Agrawal, V.D. Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB® . J Electron Test 28, 869–875 (2012). https://doi.org/10.1007/s10836-012-5332-1

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-012-5332-1

Keywords

Search

Navigation